ENC28J60 study notes--part 1th __enc28j60

0. Relevant informationRelated materials include other highlights and code warehouse "embedded TCP IP data Rollup" "ENC28J60 Learning Notes-Index" "Part 1th" "Part 2nd" "Part 3rd" "Part 4" "Stm32net Learning Notes-index" UI P Learning Notes "LWIP learning notes--stm32 enc28j60 transplant and Getting Started"
1 Preface

Embedded Ethernet development can be divided into two parts, one is the use of Ethernet transceiver chip, one is the implementation of embedded Ethernet protocol stack. The use of Ethernet transceiver chips than the use of serial transceiver chip more complex, the market on the circulation of a wide range of Ethernet transceiver chip types are many, there are SPI interface enc28j60, there are also the form of rtl8019s,cs8900a and so on. Embedded Ethernet protocol Stack has the well-known UIP protocol stack, LWIP protocol stack, and other embedded expert developed the protocol stack. Whether it is hardware or software, can not be divided into high and low, suitable for the project needs is the best. 1.1 Reasons for writing

Explain the reasons for my writing again. Previously purchased from Taobao Enc28j60, the store vowed to provide 51AVR LPC STM32 and other platform code, you can implement a Web page control led. The mind a hot bought back, buy back only found, stores provide information fragmented, difficult to understand. After turnover, found that the original enc28j60 of the code are from a local--avrnet, originated from a foreign open source project. With the most primitive code to savor, the Ethernet protocol is less mysterious. Here to say the use of enc28j60, familiar with the enc28j60 drive can be divided into several steps. The first step, through the enc28j60 transplant uIP or LWIP protocol stack, TCP or UDP communication, second, follow the Avrnet Project Walk, implement a simple Web server, running static or dynamic Web pages. Embedded Ethernet and Computer Ethernet development is different, for TCP communication, there is no socket socket, for Web programming, there is no IIS or PHP, the implementation will be relatively troublesome, but also very fun. 1.2 Information Preparation

Embedded Ethernet development is a very complex task, and it's a good idea to browse the ENC28J60 manual before you start. In addition, we need to read the TCP IP related knowledge carefully, recommend a book "Embedded Internet TCP/IP foundation, implementation and application." Embedded development is an iterative process, which refers to the Avrnet project and the relevant examples of the struggle Development Board. "Avrnet Project URL link"

Although the MCU used in the Avrnet project is ATMEGA32, it can be conveniently ported to other MCU platforms after careful reading of the source code, such as STM8, STM32 and MSP430. 2 registers and registers operation

Enc28j60 registers a lot, the operation of these registers requires a good code to organize work. In the Avrnet project, the Enc28j60 drive is decomposed into ENC28J60.h files and enc28j60.c files . H file mainly describes the basic definition of enc28j60 registers, while the C file mainly implements the operation of these registers. 2.1 Register Definition

First, analyze the ENC28J60.h header file. Reading the data manual, you will find that the number of enc28j60 registers, through analysis and collation, operation of ENC28J60 registers need to pay attention to the following 3 points.

"1" has three different forms of registers-- control registers , Ethernet registers and PHY registers , with different registers beginning with different letters, distinguished by E, MA and Mi. The operation of these three different registers requires a different combination of commands.

"2" registers are distributed in 4 different bank , that is, there are registers with the same address, but these registers are in different partitions, the correct bank must be checked before the register is operated.

"3" Although there are 4 bank, but there are 5 registers in 4 bank positions are the same, they are eie, EIR, Estat, ECON1, ECON2.

In the Avrnet project, registers are defined as 8-bit lengths, and the 8-bit length contains three parts, the address bit7 (highest bit) is used to differentiate PHY and Mac registers, and the PHY registers operate most specifically; address bit6 and BIT5 to differentiate the bank, 2-bit space exactly distinguishes 4 bank, and the last 5 bits of the address are the address of the register. In this way, you can distinguish all registers. Lists a few lines of code. Because the header file is very long, it is not all listed.

Bank0 Register
#define ERDPTL            (0x00|0x00)
#define ERDPTH            (0x01|0x00)
#define EWRPTL            (0x02| 0x00)
//BANK1 Register
#define EHT0              (0x00|0x20)
#define EHT1 (              0x01|0x20)
#define EHT2              ( 0x02|0x20)
//BANK2 Register
#define MACON1           (0x00|0x40|0x80)
#define MACON2           (0x01|0x40|0x80)
#define MACON3           (0x02|0x40|0x80)
BANK3 Register
#define MAADR1           (0x00|0x60|0x80)
#define MAADR0           (0x01|0x60|0x80)
#define MAADR3           (0x02|0x60|0x80)

For example, Erdpth is an Ethernet register located in BANK0, the first digit 0x01 represents the specific address in bankx, the address is 0x01, the second number 0x00 represents the bank number, and the bank address is 0;eht1 for the control register located in BANK1, The first 0x01 represents the specific address in bankx, the address is 0x01, and the second 0x20 represents the bank number, where the bank number is 1. Please note that because the bank number is saved in BIT6 and BIT5, this is 0x20 instead of 0x10;macon2 for the Ethernet register located in BANK2, the first digit 0x01 represents the register address in the Bankx, and the second number 0x40 represents the bank number, The bank number is 2, and the third digit 0x80 represents the register as an Ethernet register or PHY register, which is a special operation.

In order to facilitate register operation, the header file also defines a register address operation mask, in simple terms, you need to see which bits, do not need to see which bits.

/* Register Address Mask *        /#defineADDR_MASK 0x1F
/* Storage area Mask
/#defineBANK_MASK        0x60
/* mac and MII Register mask * *
#defineSPRD_MASK         0x80

In addition, there are 5 special control registers, Eie,eir,estat,econ2 and ECON1.

/* Key Register/*
#defineEIE                     0x1b
#defineEIR                     0x1c
#defineESTAT                   0x1d
#defineECON2                  0x1E
#defineECON1                  0x1F

2.2 Register Operation Command

A register operation command can also be called a register operation code. In order to implement the register operation, ENC28J60 defines the 6+1 Register operation command (opcode). Operation related registers have at least Read Register command, write register command, send or receive Ethernet data must have write buffer command or read buffer command, in order to speed up operation, for some control registers can also have position or clear 0 of a bit command; Finally, add a software reset command, icing on the cake.

/* Read Control Register/*
#define ENC28J60_READ_CTRL_REG         0x00/
* Read buffer/
#define ENC28J60_READ_BUF_MEM          0x3a /
* Write control register//
#define ENC28J60_WRITE_CTRL_REG        0x40/
* Write buffer * *
#define Enc28j60_write_buf_mem         0x7a/
* bit field placement/
#define ENC28J60_BIT_FIELD_SET         0x80/
* bit domain Clear 0 * * *
#define Enc28j60_bit_ FIELD_CLR         0xa0/
* System reset */
#define ENC28J60_SOFT_RESET            0xFF

2.3 Receive and send buffer allocations

The receiving and sending of Ethernet data can not be separated from the ram inside the drive chip, but also called the hardware buffer. The enc28j60 includes a hardware buffer of 8 K, part of which is used by the receiving buffer and the other part for the send buffer . The ultimate purpose of control enc28j60 is to manipulate the hardware buffer. When executing the Ethernet Send command, the data is populated into the sending buffer, and the relevant registers are sent to transmit the Ethernet data, and the Ethernet data input events are obtained by querying the relevant registers or external interrupts, and then reading the relevant data from the receiving buffer.

(1) Dividing the buffer into two parts. Dividing the 8K hardware buffer into two parts requires at least four parameters, the receiving buffer needs a starting address and an end address to describe, and the sending buffer needs a starting address and an end address to describe. Ideally, two buffers fully occupy 8K of hardware buffers, making the perfect use of this space. Because the register length of the enc28j60 is 8 bits and the hardware buffer size is 8K, the 4 addresses mentioned above need 8 registers to be fully described, and a single address needs to be divided into 8-bit and 8-bit. In the Avrnet project, the receive buffer is larger and the sending buffer is smaller. In the Ethernet protocol, the maximum packet length is 1518 bytes, while the tabloid length is 60 bytes. The send buffer is equal to or slightly greater than 1518 bytes, and the remaining portion is all allocated to the receive buffer. Receive buffer is also considered the ability to handle the AVR is limited, if a certain point in time to receive a number of Ethernet packets, you can first put the message idle and hardware buffer, to the MCU idle and then removed from the buffer.

/* Receive buffer start address                //#define RXSTART_INIT 0x00
/* Receive buffer Stop address * *
#define RXSTOP_INIT                 (0x1fff-0x0600-1) c5/>/* Send buffer start address send buffer size of about 1500 bytes
/* * #define TXSTART_INIT                (0x1fff-0x0600)/
* Send buffer Stop address * *
#define Txstop_init                 0X1FFF

Figure 2.1 Hardware buffer structure

(2) for the sending buffer, you need to specify the send buffer write pointer, use the write buffer command to manipulate that part of the buffer, the address of the write pointer will grow, and if you encounter an ending address, return to the starting address. It is a bit more complex for the receive buffer, which must be specified before each read, and the start address of the buffer read pointer, based on the code above, is 0, and the read pointer address of the next read operation needs to be computed immediately after the first read operation. enc28j60 Read the buffer, the content is not all Ethernet load, before the Ethernet load also has the next packet's address pointer (two bytes), receive the status vector (4 bytes), then the "real" Ethernet load, which includes the target MAC address, The source MAC address, packet type, and so on, and finally the CRC checksum byte.

Figure 2.2 Receiving packet structure