Error When fftv5.0 IP core is used in ISE

Source: Internet
Author: User
Tags xilinx ise

Today, we want to generate a 16384-point FFT core, which uses ise10.1. However, there is always an error. The error is as follows:

Generating IP...
Warning: SIM: 216-the chosen IP does not support a VHDL behavioral model, generating a VHDL structural model instead. warning: SIM: 217-the chosen IP does not support a OpenGL behavioral model, generating a OpenGL structural model instead. error: coreutil-exception caught when running XST synthesis!
Error: coreutil-failure to generate output products
Warning: coreutil-default charset GBK not supported, using ISO-8859-1 Instea
Error: coreutil: 424-An error occurred while running Java. Please examine the console or coregen log file for a specific IP related error.
For more information please search the Xilinx answers database for this error: http://www.xilinx.com/supportFinished generating.
Error: SIM: 57-error found during generation
Warning: The originally identified core 'fft _ 000000' was not created.
If you changed the name in the customization dialog, you'll need to add that core to your project using Add source...

 

When generating an IP core, the specific settings are as follows:

 

 

Baidu and Google did not find any specific solutions. There are several directions as follows:

(1) Core generator-error messages "cocould not reserve enough space for object Heap" and "cocould not create the Java Virtual Machine"

 

Link: http://china.xilinx.com/support/answers/20708.htm

 

This post mainly refers to modifying the Java parameter in file -- preferences in core generator. The default value is 1024 mb. It cannot exceed 512 MB in windows, but I modified it and the error is still ......

 

(2) [FPGA] Xilinx ise ip Core generation problem

Link:

Http://topic.csdn.net/u/20090308/10/8e11c3d3-9348-4a3a-820e-274ba9d9a847.html

 

This post mainly refers to the low Java version or the small memory size, but my memory usage is very low now. What does the Java version mean? How can I upgrade it?

 

(3) 10.1 core generator-white space in project directory causes "error: coreutil-failure to generate output products"

Link: http://www.xilinx.com/support/answers/30515.htm

 

This post mainly refers to the fact that there is no space in the storage directory and there is no space in my directory. However, it is worth noting that for the installation of ISE or other associated software, the installation directory cannot contain spaces, and the project directory cannot contain spaces ......

 

(4) 10.1 core generator-"error: coreutil-failure to generate output products"

Link: http://www.xilinx.com/support/answers/23574.htm

 

This post indicates that the IP address core cannot be named with two underscores (_ IFFT), for example, FFT _ IFFT, but this problem does not exist here ......

 

Ah, there is no way. Later, I changed the parameter when generating the IP address core. First, I used the default parameter generated by the IP address core. Er, everything went fine at last ......

Then, change the transform length to 16384. The other parameters are default. Er, the result is also normal ......

Finally, we changed the other parameters according to our own needs to generate everything is normal ......

However, when the input data width and Phase Factor witdth are changed from 16 to the 20 required by the user, the error is ......

 

I don't know the specific reason. Is there too much resource occupation? I don't know. I asked a senior person who has done this job. He pointed out that he also encountered this problem at the time. He did not solve the fftv5.0 IP core, but there is no problem when using v3.2. Besides, there is no difference in functionality between the two versions of IP cores ......

 

So farSolutionFound:Using fftv3.2's IP core is okay ......

 

But how can I use the fftv3.2 IP core in the ise10.1 environment? What is the default V5.0 IP core? The method is as follows:

Open the core generator as follows:

Open "core generator" from the Start Menu. The specific path is"Start -- all programs -- Xilinx ISE design suite 10.1 -- ise -- accessories -- core generator"In Ise, you can click any generated IP address in the sources area and double-click manage cores under core generator in the processes area ......

 

 

 

As shown in, select Show option in the toolbar as all versions. The default value is latest versions, indicating the latest version. After selecting all versions, we can find the IP core of fftv3.2, as shown in. Double-click "Fast Fourier Transform 3.2" to open the IP Core generation wizard. Modify the parameters as needed. Show, there is also an option here: All Versions incl. Obsolete, which means all versions and contain outdated IP cores ......

 

Close the core generator after generation. At this time, the generated IP core may not be displayed in the project, but in fact it has been generated and added to the project. In this case, you can close the project and re-open it or press F5 to refresh and display it ......

 

Regarding the fftv5.0 error, I had to find a solution in this way. I don't know if it is a bug in the IP core software. I hope you can solve it ......

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