Error:ngdbuild:604-logical block ' inst_edksub/proc_sys_reset_0 ' with type ' proc

To do a very simple test

The function of invoking EDK's symbol,edk in Sch in Ise is also simple, that is, the CPU prints a string of characters

First, I built an ISE project
Re-build a source Sch type and set it to the top level, named Top.sch
Re-build a source type of embedded processor, named Mycpu
Then EDK automatically open, I add peripherals according to the wizard, set the clock until finish
Then under EDK generate Netlist, generate Lib and bsp,builder all user app.
Then go back to Ise, select MYCPU, create schematic symbol, and add the symbol to Top.sch
Add port, Constrain pin
Final synthesis, generating bit

But when we get to translate, I can't get through it.

Report the following error

Software is version 12.2

Processing BMM file "edkbmmfile.bmm" ...
error:ngdbuild:989-failed to process BMM information edkbmmfile.bmm
Checking Expanded design ...
Error:ngdbuild:604-logical block ' microblaze_0/proc_sys_reset_0 ' with type
' Proc_sys_reset_0_wrapper ' could not being resolved. A Pin name misspelling can
Cause this, a missing edif or NGC file, case mismatch between the block name
And the EDIF or NGC file name, or the misspelling of a type name. Symbol
' Proc_sys_reset_0_wrapper ' isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' microblaze_0/mdm_0 ' with type
' Mdm_0_wrapper ' could not being resolved. A pin name misspelling can cause this,
A missing EDIF or NGC file, case mismatch between the block name and the EDIF
or NGC file name, or the misspelling of a type name. Symbol ' Mdm_0_wrapper '
Is isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' microblaze_0/clock_generator_0 ' with type
' Clock_generator_0_wrapper ' could not being resolved. A Pin name misspelling can
Cause this, a missing edif or NGC file, case mismatch between the block name
And the EDIF or NGC file name, or the misspelling of a type name. Symbol
' Clock_generator_0_wrapper ' isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' microblaze_0/rs232 ' with type
' Rs232_wrapper ' could not being resolved. A pin name misspelling can cause this,
A missing EDIF or NGC file, case mismatch between the block name and the EDIF
or NGC file name, or the misspelling of a type name. Symbol ' Rs232_wrapper '
Is isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' Microblaze_0/lmb_bram ' with type
' Lmb_bram_wrapper ' could not being resolved. A pin name misspelling can cause
This, a missing edif or NGC file, case mismatch between the block name and
The EDIF or NGC file name, or the misspelling of a type name. Symbol
' Lmb_bram_wrapper ' isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' MICROBLAZE_0/ILMB_CNTLR ' with type
' Ilmb_cntlr_wrapper ' could not being resolved. A pin name misspelling can cause
This, a missing edif or NGC file, case mismatch between the block name and
The EDIF or NGC file name, or the misspelling of a type name. Symbol
' Ilmb_cntlr_wrapper ' isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' MICROBLAZE_0/DLMB_CNTLR ' with type
' Dlmb_cntlr_wrapper ' could not being resolved. A pin name misspelling can cause
This, a missing edif or NGC file, case mismatch between the block name and
The EDIF or NGC file name, or the misspelling of a type name. Symbol
' Dlmb_cntlr_wrapper ' isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' microblaze_0/dlmb ' with type ' dlmb_wrapper '
Could not being resolved. A pin name misspelling can cause this, a missing edif
or NGC file, case mismatch between the block name and the EDIF or NGC file
Name, or the misspelling of a type name. Symbol ' Dlmb_wrapper ' is not
Supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' microblaze_0/ilmb ' with type ' ilmb_wrapper '
Could not being resolved. A pin name misspelling can cause this, a missing edif
or NGC file, case mismatch between the block name and the EDIF or NGC file
Name, or the misspelling of a type name. Symbol ' Ilmb_wrapper ' is not
Supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' microblaze_0/mb_plb ' with type
' Mb_plb_wrapper ' could not being resolved. A pin name misspelling can cause
This, a missing edif or NGC file, case mismatch between the block name and
The EDIF or NGC file name, or the misspelling of a type name. Symbol
' Mb_plb_wrapper ' isn't supported in target ' spartan3a '.
Error:ngdbuild:604-logical block ' microblaze_0/microblaze_0 ' with type
' Microblaze_0_wrapper ' could not being resolved. A Pin name misspelling can
Cause this, a missing edif or NGC file, case mismatch between the block name
And the EDIF or NGC file name, or the misspelling of a type name. Symbol
' Microblaze_0_wrapper ' isn't supported in target ' spartan3a '.
Partition Implementation Status
-------------------------------
No partitions were found in this design.
-------------------------------
Ngdbuild Design Results Summary:
Number of Errors:12
Number of warnings:0
Total REAL time to Ngdbuild completion:3 sec
Total CPU time to Ngdbuild completion:3 sec
One or more errors were found during ngdbuild. No NGD file would be written.
Writing ngdbuild log file "Top.bld" ...
Process "Translate" failed

Then I saw the official explanation.

Http://www.xilinx.com/support/answers/38262.htm

In the ISE12.2 version, Ise only copied the top-level NGC file, which is MYCPU.NGC, and the top-level MYCPU also contains other NGC files, so it can not be found, error.

The workaround is to add the Mycpu module in front of

(* Box_type = "User_black_box" *)

Such as:

(* Box_type = "User_black_box" *)
Mycpu My_cpu_moudle (. Fpga_0_clk_1_sys_clk_pin (SYS_CLK),
. Fpga_0_rst_1_sys_rst_pin (Sys_rst_n),
. Fpga_0_rs232_rx_pin (UART_RXD),
. Fpga_0_rs232_tx_pin (UART_TXD),
. Led_out_gpio_io_o_pin (Led_out[0:3]));

You can do it.

Superx-man explained that:

"You know we call the internal structure of the IP core is confidential, that is, black BOX, add this sentence, that is, pointing to the things you import, without adding, the directivity is not clear, so the error said can not find."

The netizen Toto no worries also gives the solution method

Under the processes bar in Ise, select Translate, right-click Process propreties .....

The Translate Properties dialog box pops up,

Add the path to the implementation subdirectory of the EDK project in-SD macro search Path

You can do it.

The NGC generated by EDK is in the implementation directory.

Here is the address of the original post discussion:

Http://bbs.21ic.com/icview-213795-1-1.html

Note: Http://www.xilinx.com/support/answers/38262.htm can refer to the Xilinx official website