Ethernet Chip w3100a to w3150a+ porting notes (i)

Recently many users consulted w3100a, because w3100a has been discontinued. In this hope to introduce you, w3100a can be transplanted to other chips and ways, for you to better expand the use of your project, look forward to help you. Let me introduce you to the first part of the article today.

This porting note describes the issues that designers and programmers should pay attention to during the w3100a to w3150a+ migration. For more information on w3150a+, please refer to the w3150a+ data sheet.

1 vs 1.1 benefits and challenges of porting

This part emphasizes the many advantages and problems involved in the process of w3100a to w3150a+. W3150a+ provides a higher level of performance in maintaining many w3100a features. Here are the benefits of porting to w3150a+:

• Higher cost performance
• More advanced levels of integration
• Increase the TX Idle size register and RX received size registers. Users can read directly and no longer need to calculate their values.
• The TCPSEQ and ACK codes are processed automatically. Users no longer need to calculate their values.
• New features (Pppoe/igmp/spi interface/heartbeat pack, etc.)
• Use standard drive libraries to facilitate future porting of W5100. The w3150a+ and W5100 Drive libraries are fully compatible. Therefore, the user does not need to consider firmware changes during the migration from w3150a+ to W5100.

The following are some of the differences that may cause problems during the w3100a to w3150a+ migration:

• Pin assignment is different. See section II, "Hardware Considerations".
• Library migration. There are some differences between the w3100a and w3150a+ drive libraries, see the third section, "Software Considerations".

1.2 Summary and Feature comparison table

Table 1 contains some feature comparison information for w3100a and w3150a+

Table 1 Comparison of w3100a and w3150a+

2Hardware Considerations 2.1 Voltage

Are 3.3V.

2.2 TCP/IP Core

All two chips use the Wiznet world's only hardware IPv4 core. However, the w3150a+ kernel has been updated and made up for weaknesses in w3100a errata and defects, "w3100a errata and Defects". You can click on the following link to use:

Http://www.wiznet.co.kr/upload_files/referencefiles/w3100a_errata_limitation_list1[2][0].pdf

2.3 Package and PIN distribution

A) two chips are LQPF64

b) pin Distribution:

Figure 1 shows the pin distribution of the w3100a and w3150a+. See red Notes for different sections.

Figure 1 Pin assignment Considerations when migrating w3100a to w3150a+

• " " means "remove function"
• "√" means "no change"
• "<-+ comment" means "replacement part"

Pins 28, 37, and 57 are 1.8 V power-related pins in the pin assignment of the w3150a+. See Figure 2

Figure 2. Reference circuit for 1.8v power input

2.4 Interface 2.4.1 Host interface

The W3100A supports MCU bus interface and I²c interface, however the w3150a+ supports MCU bus interface and SPI interface.

Therefore, if you previously used the I²c interface to communicate, you can now use the SPI of your main MCU to connect the w3150a+. SPI is a 4-wire interface that is now very easy to use universally. The SPI interface can also be simulated with Gpio. If you use the MCU bus interface, except for a few hardware modifications, the rest of the work is simply a very simple drive porting. See table 2.

Table 2 Main Interface considerations

2.4.2 Mii Interface

W3100A supports two MII types. One is serial Mii, the other is half-bit Mii, but w3150a+ only supports half-bit Mii. Therefore, if you are currently using Serial Mii mode, you will need to adjust your PHY chip to a half-bit type. In addition, the w3150a+ has two independent pins: RXDV and CRS. The user should connect the pin RXDV (no.44) to the pin RXDV (PHY chip end) connection, as well as the pin CRS (no.47) connection to the PIN CRS (PHY chip side).

2.5 System Characteristics 2.5.1 Clock

The w3100a has two clock pins (4th pins and 33rd pins. However, the w3150a+ removes the external clock mode. Therefore, the w3150a+ has only one clock source: 25MHz (no.35 pin).

2.5.2 System restart

Two chips support both hardware and software reboots.

• Hardware restart signal, w3100a is high point flat effective, but w3150a+ is low active
• software reboot, all by writing" 1 "to 7th bit in the specified register, to achieve this function.

The w3100a is in the C0_CR register (offset address 0x00). The w3150a+ is in the Mr Register (offset address 0x00).

2.5.3 Register read/write timing

W3100A includes direct & Indirect mode support for 6 MCU bus interface modes, however w3150a+ only supports 2 MCU bus interface modes. In this case, there is a huge difference in reading and writing timing.

When migrating from w3100a to w3150a+, the user should use the timing of the w3150a+. For more information, see the w3150a+ Data sheet: 7.4.2 Register/Memory Read timing & Register/Memory Write timing.

2.5.4 TX/RX Cache

Each of the two chips has a 16Kbytes tx/rx cache. Therefore, you do not have to consider the cache limit in the migration.

2.6 Register Address mappings

The w3100a consists of a control register, a pointer register, a system register, a channel register, and a tx/rx cache, however, the w3150a+ consists of a generic register, socket register, and TX/RX cache.

Figure 3. Register mappings for w3100a and w3150a+

Figure 3. Register mappings for w3100a and w3150a+

We continue tomorrow, thanks for reading!

Ethernet Chip w3100a to w3150a+ porting notes (i)