[Excerpt] About starting from NAND Flash

Http://blog.chinaunix.net/u2/69674/showart_1212448.html

The operating system uses S3C2410. See the appendix start. S. The section about NAND Flash startup has been puzzling. It should be mapped to ngcs0 In the first 4 kb when it is started from NAND Flash.CodeStoreProgramThe program provided by the file is like copying the K code from NAND to the place where the resetentry starts, that is, the address is 0, then copy the resetentry to ram, but ngcs0 seems to only have a 4 kB RAM zone at this time. How can I store the KB code. hope you have a finger. Thank you!

The difference between the two commands is as follows:

LDR r0, = _ entry and ADR r0, _ entry

The former is the absolute address generated according to the load address during compilation, and the latter is the addressing relative to the current PC after disassembly. For example, if the RO address is set to 0x30000000 in ads, the value transmitted by the former to R0 is 0x30000000, while the value transmitted by the latter to R0 depends on the current PC. Generally, when starting from ngcs0, the value transmitted to R0 is 0.

amsung S3C2410 supports nor flash and nand flash Boot. You can set the Boot Mode on the SBC-2410X by using the bootsel Jumper:
|------ |
| .. | boot from NAND Flash
|------ |
.. boot from nor flash
Note:
(1) the bootsel jumper is connected between the "Serial Port" and "USB slave interface"
(2) with a "Jumper card", which indicates that it is started from NAND Flash. Unplug the patch cord to start from nor flash.

Parse understands that nor flash is of low capacity, fast speed, and stable. It is suitable for program memory. The total capacity of NAND Flash is large and suitable for data storage. It cannot be started from NAND Flash. The read/write sequence of NAND Flash cannot be directly generated by ARM hardware. To read and write NAND Flash, it must be implemented through a program, obviously, we can see that NAND Flash only has eight data address interfaces for data address reuse. 2410/2440 can be directly started from NAND Flash because it maps 4 K in front of NAND to the space of SRAM.

First, you should first understand the types of Flash ROM:

The nor flash Address line is separated from the data line. The address and control signal are generated, and the data comes out.

The NAND flash Address line and the data line must be controlled by a program before data can be exported.

In general, it means that the address alone cannot be used. You must first run the command and then the address to read the NAND data. It is also completed in a bus.

The conclusion is that arm cannot be started directly from NAND. NAND flash can be used only after the program is loaded.

The loader can only be from the mask Rom or nor flash.

 

Nand and nor flash designers must carefully choose flash when using flash.

-- M-Systems Company Arie tal

Nor and NAND are two major non-loss flash technologies on the market. Intel first developed nor Flash technology in 1988, which completely changed the previous situation where EPROM and EEPROM were integrated. Next, in 1989, Toshiba published the NAND Flash structure, emphasizing reducing the cost per bit and higher performance, and easily upgrading it through interfaces like disks. However, after more than a decade, a considerable number of hardware engineers are still confused about nor and NAND Flash. Flash memory can often be used with nor memory. Many insiders do not know the advantages of NAND Flash compared with nor, because in most cases, Flash is only used to store a small amount of code, so nor flash is more suitable for some. Nand is an ideal solution for high data storage density. Nor features in-chip execution (xip, execute in place), so that applications can run directly in flash memory without having to read the code into system Ram. Nor transmission efficiency is very high, in 1 ~ The small size of 4 MB has high cost efficiency, but the low write and erase speeds greatly affect its performance. The NAND structure provides a very high unit density, achieves a high storage density, and writes and erases quickly. The difficulty of using NAND lies in Flash management and special system interfaces. Compared with flash memory, flash memory is non-easy to lose memory. You can erase and re-program memory unit blocks called blocks. Any write operation on the flash device can only be performed in an empty or erased unit. In most cases, the operation must be erased before writing. It is very easy for the NAND device to perform the erasure operation, and nor requires that all the bits in the target block be written to 0 before the erasure. Since the nor device is erased with 64 ~ For blocks of KB, the time for performing a write/erase operation is 5 S. In contrast, the erased NAND device is 8 ~ For 32 KB blocks, it takes up to 4 ms to perform the same operation. When the block size is erased, the performance gap between nor and nadn is further extended. Statistics show that for a given set of write operations (especially when updating small files ), more erasure operations must be performed in the nor-based unit. In this way, when selecting a storage solution, the designer must weigh the following factors.

● Nor reads faster than NAND.

● NAND writes much faster than nor.

● NAND's 4 Ms erasure speed is far faster than nor's 5s.

● Most write operations require erasure first.

● NAND has fewer erased units and fewer erased circuits.

Interface difference nor Flash has an SRAM interface, which has enough address pins to address and can easily access every byte in it.

Nand devices use complex I/O ports to access data in a serial manner. Different products or vendors may use different methods. Eight pins are used to transmit control, address, and data information. Nand read and write operations use 512 bytes of blocks, which is a bit like hard disk management. Naturally, NAND-based memory can replace hard disks or other Block devices. Capacity and cost the unit size of NAND Flash is almost half the size of the nor device. Due to the simpler production process, the NAND structure can provide higher capacity within the given mold size, the price is reduced accordingly. Nor flash occupies 1 ~ Most of the 16 MB flash memory market, while NAND Flash is only used in 8 ~ Among the MB products, this also shows that nor is mainly used in code storage media. NAND is suitable for data storage. NAND shares the largest share in the compactflash, secure digital, PC cards, and MMC memory cards markets. Reliability and durability when using the flahs Media, a major concern is reliability. Flash is a suitable storage solution for systems that need to expand MTBF. The reliability of nor and NAND can be compared in terms of life (durability), bit switching and bad block processing. Lifetime (durability) in nand flash memory, the maximum number of writes per block is 1 million, and the number of nor writes is 100,000. In addition to having a block erasure cycle of 10 to 1, the typical NAND block size is eight times smaller than that of the nor device, each NAND memory block is deleted less frequently within a given period of time. All flash devices suffer from bit switching. In some cases (rarely, Nand occurs more often than nor), a bit is reversed or reported to be reversed. One-bit changes may not be obvious, but if it occurs on a critical file, this small fault may cause system downtime. If there is only a report problem, it may be solved by reading multiple times. Of course, if this bit changes, you must use error detection/error correction (EDC/ECC) Algorithm . The problem of bit inversion is more common in nand flash memory. The NAND supplier recommends using the EDC/ECC algorithm when using nand flash memory. This problem is not fatal when using NAND to store multimedia information. Of course, if you use a local storage device to store operating systems, configuration files, or other sensitive information, you must use the EDC/ECC system to ensure reliability. Bad blocks handle random distribution of Bad blocks in NAND devices. I have tried to eliminate bad blocks before, but I found that the yield rate is too low, the cost is too high, and it is not cost-effective at all. The NAND device needs to initialize the media to detect Bad blocks and mark them as unavailable. In an existing device, a high failure rate may occur if this processing is not performed in a reliable way. It is easy to use and can directly use nor-based flash memory. It can be connected like other memory and can directly run code on it. Due to the need for I/O interfaces, Nand is much more complicated. The access methods for various NAND devices vary from manufacturer to manufacturer.

When using the NAND device, you must first write the driver to continue other operations. Writing information to a NAND device requires considerable skill, because designers must not write information to Bad blocks, which means virtual ing must be performed from beginning to end on the NAND device. Software Support: when discussing software support, we should distinguish basic read/write/erase operations from high-level software for disk simulation and flash memory management algorithms, including performance optimization. Running code on the nor device does not require any software support. When performing the same operation on the NAND device, the driver is usually needed, that is, the memory technology driver (MTD ), the NAND and nor devices require MTD for write and erase operations. Fewer MTDS are required to use the nor device. Many vendors provide more advanced software for the nor device, including the trueffs driver of the M-system, this driver is used by Wind River system, Microsoft, QNX software system, Symbian, Intel, and other vendors. The driver is also used to simulate diskonchip products and manage nand flash memory, including error correction, Bad Block Processing, and loss balancing.

 

Samsung 2410 can start a program from NF. It will copy the first 4 kb of the first block to the internal SRAM and execute it from the SRAM. That is to say, you need to write a boot program with a length less than 4 kb, the function is to copy the main program to the SDRAM for running (NF address is not linear, the program cannot run directly, and must be copied to linear RAM)
Basic principle of starting U-BOOT from NAND Flash
Certificate --------------------------------------------------------------------------------------------------------------------------------------------------------------

Top 4 K problems

If S3C2410 is configured to start from NAND Flash (configured by hardware engineers on the circuit board), the NAND Flash Controller of S3C2410 has a special function, the NAND Flash Controller automatically moves the first 4 k Data on the NAND flash to the 4 K internal RAM of the CPU, and sets 0x00000000 as the starting address of the internal RAM, the CPU starts from the internal RAM 0x00000000 position. No program interference is required in this process. What programmers need to do is to put the core Startup Program in the first 4 K of NAND Flash.

Program startup schedule

Since the code for the NAND Flash Controller to move from the NAND flash to the internal RAM is limited, in the first 4 K of the startup code, we have to complete the core configuration of S3C2410 and move the rest of the startup code (U-BOOT) to ram for running.

U-boot source code does not support starting from NAND flash, but S3C2410 supports starting from NAND Flash, Development Board (sbc-2410x) after power-on, the S3C2410 command saves the first 4 K of NAND Flash (some features of U-boot-copy function-copy the content in the NAND flash to the SDRAM) copy it to the SRAM (the SRAM In the S3C2410 chip ). In this case, you need to modify the U-boot source code and add the U-boot function: Enable U-boot to copy itself to the sdram on the development board after obtaining the execution right, so that the processor can execute U-boot.
The commands, addresses, and data of NAND Flash are sent through the I/O port and the pins are reused. The advantage of this is that the number of NAND Flash pins can be significantly reduced, in the future, if designers want to replace NAND Flash with higher density and larger capacity, they do not have to change the circuit board.

NAND Flash cannot execute the program. The reason is as follows:

1. NAND flash itself is connected to the controller rather than the system bus. After the CPU is started, the command is executed. If it is srom, nor flash, and so on, the CPU sends an address to obtain and execute the command, but the NAND Flash cannot, because NAND Flash is used for Pin multiplexing, it has its own set of time sequence, so that the CPU cannot obtain executable code and the system cannot be initialized.

2. NAND Flash is a sequential access device. Without random access, the program cannot be split or redirected, so how do you design the program.

U-BOOT supports arm, PowerPC and other architectures of the processor, also supports Linux, NetBSD, VxWorks and other operating systems, mainly used to develop embedded system initialization code bootloader. Bootloader is a piece of code executed before the chip is reset and enters the operating system. It completes the transition from hardware startup to operating system startup, and provides a basic operating environment for operating the operating system, such as initializing the CPU, stack, and memory system. Its function is similar to that of the BIOS of a PC.

Operating principle of NAND Flash

The nand flash memory of the S3C2410 Development Board consists of the nand flash memory controller (integrated into the S3C2410 CPU) and the nand flash memory chip (k9f1208u0a. To access data in the nand flash memory chip, you must use the nand flash memory controller to send commands. Therefore, nand flash memory is equivalent to a peripheral of S3C2410, not in its memory address zone.
The data storage structure of nand flash memory (k9f1208u0a) is divided into: 1 device = 4096 blocks; 1 device = 32 pages/row (page/row ); 1 page = 528b = data block (512b) + OOB block (16b)
On each page, the last 16 bytes (also known as OOB) are set after the NAND Flash command is executed. The remaining 512 bytes are divided into the first half and the second half. You can use the nand flash memory command 00 h/01 H/50 h to locate the front half, back half, and OOB respectively, and use the built-in pointer of the nand flash memory to point to the respective first address.
The Operation Features of nand flash memory are as follows: The minimum unit of the erasure operation is block. each bit of the nand flash memory chip can only change from 1 to 0, but not from 0 to 1, therefore, the corresponding block must be erased before writing data to it; the 6th bytes of OOB are the bad fast sign, that is, if it is not a bad block, the value is ff; otherwise, it is a bad block; except for OOB 6th bytes, the first three bytes of OOB are usually used to store the hardware ECC (Verification register) Code of the nand flash memory;

Design idea of starting U-BOOT from nand flash memory

If S3C2410 is configured to start from the nand flash memory, after power-on, the S3C2410 nand flash memory controller will automatically move the first 4 k Data in the nand flash memory to the internal RAM, set 0x00000000 as the starting address of the internal RAM, And the CPU starts from the 0x00000000 position of the internal RAM. Therefore, the core startup program should be placed in the first 4 K of nand flash memory.
Since the code for the NAND Flash Controller to move from the nand flash memory to the internal RAM is limited, the core configuration of the S3C2410 must be completed in the first 4 K of the startup code, and move the remaining part of the startup code to ram for running. In the U-BOOT, the main work completed in the first 4 k is the first phase of the U-BOOT startup (stage1 ).
According to the U-BOOT execution flow chart, it is known that to start the U-BOOT from the nand flash memory, first need to initialize the nand flash memory, and the U-BOOT from the nand flash memory to the ram, finally, the U-BOOT needs to support command operations for NAND Flash.

Development Environment

The hardware environment of the target board in this design is as follows: CPU is S3C2410, SDRAM is hy57v561620, and NAND Flash is 64 MB k9f1208u0a.
The host software environment is redhat9.0, u-boot-1.1.3, GCC 2.95.3. Modify makefile for the U-BOOT, add:
Wch2410_config: unconfig @./mkconfig $ (@: _ Config =) arm ARM920T wch2410 null s3c24x0
Name the Development Board wch2410, and perform the following operations in sequence:
Mkdir board/wch2410
CP board/smdk2410 board/wch2410
MV smdk2410.c wch2410.c
CP include/configs/smdk2410.h include/configs/wch2410.h
Export Path =/usr/local/ARM/2.95.3/bin: $ path
Last run:
Make wch2410_config
Make all arch = arm
Generate the u-boot.bin, which passes the test compilation.

Specific design
Enable Program Design for nand flash memory
Because the U-BOOT Entry Program is/CPU/ARM920T/start. s, so you need to add the nand flash memory reset program in the program, and realize the function of moving the U-BOOT from the nand flash memory to the RAM program.
Add config_s3c2410_nand_boot to/include/configs/wch2410.h, as shown below:
# Define config_s3c2410_nand_boot 1 @ support starting from nand flash memory
Then, add/CPU/ARM920T/start. s
# Ifdef config_s3c2410_nand_boot
Copy_myself:
MoV R10, LR
LDR sp, dw_stack_start @ start address of the installation Stack
MoV FP, #0 @ initialize frame pointer register
BL nand_reset @ jump to reset C function to execute, execute nand flash memory reset
.......
/* Copy the U-BOOT from NAND Flash to Ram */
LDR r0, = uboot_ram_base @ set 1st parameters: Starting address of uboot in Ram
MoV R1, #0x0 @ set 2nd parameters: the starting address of the nand flash memory
MoV R2, #0x20000 @ set 3rd parameters: length of the U-BOOT (KB)
BL nand_read_whole @ call nand_read_whole () to read data from nand flash memory to ram
Tst r0, #0x0 @ if the return value of the function is 0, the execution is successful.
Beq OK _nand_read @ compares the first 4 K content in RAM with the first 4 K content in NAND FLASH memory. If they are identical, the migration is successful.
Here, nand_reset () and nand_read_whole () are added to/board/wch2410/wch2410.c.

Support U-BOOT command Design
The support for nand flash memory in U-BOOT is mainly to realize the operation of nand flash memory in command line. Commands for implementing nand flash memory are: NAND Info (printing NAND Flash information), Nand device (displaying a NAND flash device), and NAND read (Reading nand flash memory), Nand write (write nand flash memory), Nand erease (erase nand flash memory), and NAND bad (display Bad blocks.
The main data structures used are: struct nand_flash_dev and struct nand_chip. The former includes information such as the main chip model, storage capacity, device ID, and I/O bus width. The latter is the information used for operating the NAND FLASH memory.

A. Set Configuration Options
Modify/include/configs/wch2410.h to enable the cmd_cmd_nand option in config_commands. Define the starting Register address and page size of the nand flash memory controller in the SFR area, and define the underlying interface functions of the NAND Flash command layer.
B. Add the NAND FLASH memory chip Model
Modify the following struct value assignment in/include/Linux/MTD/nand_ids.h:
Static struct nand_flash_dev nand_flash_ids [] = {
......
{"Samsung k9f1208u0a", nand_mfr_samsung, 0x76, 26, 0, 3, 0X4000, 0 },
.......
}
In this way, operations on the nand flash memory chip can be correctly performed.
C. Compile the nand flash memory initialization Function
Add the nand_init () function to/board/wch2410/wch2410.c.
Void nand_init (void)
{
/* Initialize the NAND Flash Controller and the NAND flash chip */
Nand_reset ();
/* Call nand_probe () to detect the chip type */
Printf ("% 4lu MB \ n", nand_probe (pai_nand_base)> 20 );
}
This function is called by start_armboot () at startup.
Finally re-compile the U-BOOT and the generated u-boot.bin into the nand flash memory, the target board after the power output from the serial port the following information:
U-boot 1.1.3 (Nov 14 2006-11:29:50)
U-Boot Code: 33f80000-> 33f9c9e4 BSS:-> 33fa0b28
Ram Configuration:
Bank #0: 30000000 64 MB
# Unknown flash on bank 0: Id 0 xFFFF, size = 0x00000000 = 0 MB
Flash: 0 KB
Nand: 64 MB
In: Serial
Out: Serial
Err: Serial
Hit any key to stop autoboot: 0
Wch2410 #

Conclusion
In the past, the solution of porting the U-BOOT to the arm9-platform mainly aimed at the nor flash memory in arm9-because of the structural characteristics of the nor flash, the application can run directly in its internal, without reading code into RAM, the porting process is relatively simple. The design difficulty of starting U-BOOT from nand flash memory is that the U-BOOT code needs to be moved to Ram and the U-BOOT needs to support the command operation of nand flash memory. This article describes how to implement this design and the specific procedures. After transplantation, the U-BOOT runs well in the embedded system.

references
1 du chunlei. ARM architecture and programming [M]. beijing: Tsinghua University Press, 2003
2 S3C2410 user's mannual [Z]. samsung