Experience with Modelsim for the first time

I found some materials on the Internet to learn. It seems that I think the three Modelsim simulation methods are good, and I did it step by step. The results can be imagined. The problem is one by one, after two days of exploration, I still learned something and noted it down.

First: the basic method for manipulating Modelsim

1. GUI interface (GUI), which also accepts command line input. (Suitable for cainiao)

2. Do files should be written in the Tcl footfall language. (Upgrade learning)

Second: Question about adding the Altera simulation library to Modelsim

I saw a lot of information about this on the internet, but they are old. Then I found that the library they want to add has been added to the new Modelsim version, I don't know if I don't need to manually add a simulation library. During the simulation, I only need to specify the next one. When I do the simulation of the small program of the streaming lamp, it's okay to specify the original library, other programs may need to be created and added to other libraries. The reason why I don't need to add a library is that I use Modelsim Altera edition, which contains the Altera simulation library.

Third: There are a lot of information about the three types of simulation (simulation steps are not mentioned)

First, I want to literate myself.

ModelSim is divided into SE, PE, le, Xe (Xilinx version), AE (Altera version), which are integrated in the OEM version of the design manufacturer. Simulation is divided into functional simulation (pre-simulation, RTL level), door-level simulation (after integration), timing simulation (after layout and wiring), and the latter two are also called post-simulation. Files required for functional simulation: HDL files (. v), testbench file (. v) specifies the pre-compiled library during simulation. Generally, select 220model_ver. file required for door-level simulation: testbench file (. v), the net table file generated by Quartus II (. VO OpenGL output file), specifies the pre-compiled library, usually select the relevant device, such as cycloneii_ver; the file required for timing simulation: testbench file (. v), the net table file generated by Quartus II (. VO), you must specify the latency. path of the SDO file. For example, led_inst is the alias of the top-level file in testbench. Specify the pre-compiled library. Generally, select related devices, such as cycloneii_ver. Note that the delay file needs to be copied to the root directory of the project created by ModelSim for unknown reasons, otherwise, an error occurs in the molesim simulation load.

The following is a simulated wave chart.

This is a functional simulation diagram, we can see that there is no delay output, and the clock edge is also synchronized.
This is a door-level simulation. We can see that the delay output, but the clock is synchronized along
This is a time series simulation. We can see that the delay output and the clock are no longer synchronized. Fourth: Quartus II settings

First, set the Modelsim path, as shown in figure
Then set assignment -- settings as follows:

Then, moresettings

If settings is set to on, only. VO file, off except. the VO file also has. SDO files (standard delayed output files, standard delayed files in the SDF format of Standard delay files), and so on. It is best to reset the settings for different simulations and compile them all, because if there is one in the door-level simulation folder. the SDO file seems to be faulty, and the simulation error is loaded in ModelSim. Note: The New quartue II version is no longer equipped with the simulator tool, this means that you cannot use a built-in Simulator for simulation (future versions of the Quartus II software will not support the Quartus II simulator Altera recommends using the modesim software for simulating designs ), of course, it cannot be generated internally. SDO file (a delayed file will be generated after full compilation in previous versions for simulator)

It is recommended that you do not select the run gate_level simulation automatically after compilation option, or use the eda rtl simmulation/eda gate level simmulatiao menu to perform simulation using Modelsim, instead of directly calling Modelsim in Quartus, there are at least three benefits: 1. fast. Simulation will inevitably constantly modify the design. After each design modification, The Modelsim must be integrated in Quartus II before it can be called. It takes more time and can be called only after the layout wiring is complete. In this way, it is very painful to wait each time. Instead, it is directly simulated in ModelSim. After modification, it can be simulated only after re-compilation, which is much faster. However, there is a downside, that is, the design is not necessarily comprehensive. However, as long as we follow the design rules at all times during programming and cultivate a good programming style, this disadvantage can be minimized. 2. Easy debugging. When Modelsim simulation is called in Quartus, only the input and output signals can be seen. However, it is impossible to observe the designed intermediate signal/variable, especially the internal signal/variable of the IP core. In Modelsim, direct simulation can observe any signal/variable in the design and any signal/variable in the IP core, so that the data flow we designed can be clearly expressed, it can also detect the Processing Effects of Different programming methods, greatly facilitating debugging. 3. convenient parameter modification. When simulating an IP Core in Modelsim, you must add the behavior description file of this IP core to the project. Modifying the IP core parameters in the behavior description file can easily change the IP core features.

Fifth: red lines or blue lines in Modelsim simulation

At the beginning, there was a red dot. After consulting in the QQ group, there are probably the following reasons: 1. some codes that cannot be integrated exist in the RTL level. The codes are integrated and the signals cannot be displayed. 2. the timing Simulation Clock settings are incorrect, that is, the time set in testbench must be adapted to the RTL-level description. here, by the way, the run XXX time in Modelsim is only the length of a single-step simulation, it has nothing to do with this situation; 3. some signals are not given an initial value in testbench; 4. the so-called most idiotic error, testbench accidentally describes the signal into two variables, just like rst_n and rst_n. I am such an idiot.

 

The above are just some of my questions and opinions, which may be highly different from those of everyone. They are for reference only.

 

Supplement: Generate testbench

There are two methods to generate testparts from quartuⅱ:

(1) export from the waveform file using the following method:

Open the Waveform simulation file, that is, the. vWF file, edit the input information, and click flie-> export to export the file directly.

(2) You can also generate the testbench Template Using QuartusII, processing> Start test1_templatewriter, and then enter the test information on your own.

3. Assignment> Settings> EDA tools setting> simulation, configure nativelink, click Test benches, and click New To Go To The test benchmark setting page. Set "test benchmark name" to asyn_fifo, which can be set as needed, top level module in test partition: asyn_1_o_vlg_tst, design instance name in test partition enter the name of the sample module in asyn_1_o_tb.v, add your asyn_1_o_tb.v file at the bottom, and click OK.

Note: The suffix of the testbench file in quartuⅱ is. vt. The template can be implemented through start-> Start test using template writer. The generated template file only contains port ing and port declaration. The specific functions must be edited by the designer.

4. Run the simulation. Tools> run eda simulation tool

Here, RTL simulation is a register transfer-level simulation. It is an idealized simulation that does not contain any delay information. It is usually used as a function test, also known as a front simulation or function simulation;

Gate-level simulation is a gate-level simulation, also known as post-simulation or timing simulation. It contains delay information such as Logical Circuits and layout and wiring, and is a simulation of real circuit conditions. To simulate a door-level simulation, it must be performed after fitter.

 

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Today, when Modelsim is used for a post-simulation, it is found that there is no output of the PLL. When setting different test clock frequencies, there are three situations:

(1) When the input clock cycle is less than the input clock cycle selected in the sample PLL, the following warning message is displayed during simulation:

 

Warning: Input clock freq. Is under VCO range. Cyclone iii pll may lose lock

 

(2) When the input clock cycle is greater than the input clock cycle selected in the sample PLL, the following warning message is displayed during simulation:

 

Warning: Input clock freq. Is Over VCO range. Cyclone iii pll may lose lock

 

In the above two cases, the PLL will not work normally. In the first case above, you can set a larger period for the input test clock. In the second case, you can set a lower cycle for the input test clock.

 

(3) When the input clock cycle is equal to the input clock cycle selected in the sample PLL, the following information appears during simulation:

 

Note: Cyclone iii pll locked to incoming clock

 

In this case, the PLL can work normally.

 

Based on the above three situations, I have determined that the. VO file generated after compilation contains the configurations of the PLL, such as the input frequency of the PLL. However, I also find it confusing that the frequency of the input test clock is not necessarily the same as the input clock frequency set in the sample PLL so that the PLL can work. I don't know why.

 

However, you do not need to set the frequency of the test clock to be exactly the same as the input clock of the PLL, for example, the input clock frequency of the Self-sample PLL is 400 MHz (from the device manual, the PLL input of cyclone III supports such a high frequency ), during the test, I set the frequency of the input test clock to 2.5ns, but the PLL has no output. When I change to 5ns, there will be output.

 

In addition, before the simulation, we also found the same problem, that is, if the input clock frequency of the PLL is not suitable, then the PLL will not work, but when the PLL cannot work normally, modelSim does not have any reminder. Note: Cyclone iii pll locked to incoming clock appears only when it works normally. In addition, setting the test clock frequency does not have to be the same as the output clock frequency of the PLL for normal operation.

 

I don't know the scope of the test clock frequency, so that the PLL can work normally. Hope you can give me more advice!