NOP null Operation Command
Syntax: NOP
Operand: None
Execution time: one instruction cycle
Execution Process: Except for consuming one instruction cycle, it has no impact. Therefore, it is usually used as a delay.
Status flag impact: None
Note: The instruction operation does not involve any operands and does not affect the content and status of any registers. Therefore, it is generally used as a delay.
Command example: BSF portb, 0; portb's 0th-bit output high level (1)
NOP; latency to make the level stable
Movwf transfers W register content to the data register
Syntax: movwf F
Operand: F is the low 7-bit address of the data register (0x00 ~ 0x7f)
Execution time: one instruction cycle
Execution Process: Transfers W register content to f data register, W register content remains unchanged, similar to copy
Status flag impact: None
Note: This command is used to assign values to data registers.
Command example:
Movlw 0x55; W register value assignment
Movwf data; W register value transmitted to data
Data = 0x55
Clrw W register content cleared 0
Syntax: clrw
Operand: None
Execution time: one instruction cycle
Execution Process: 0x00 → W
1 → Z
Status flag impact: Z
Note: This command clears W register content, and sets the 0 Mark Z of the parallel position.
In addition, you can use movlw 0x00 to set the W register content to 0, but this command does not affect the 0 Mark Z.
Command example: clrw; W = 0, Z = 1
Clear clrf data register content
Syntax: clrf F
Operand: F is the low 7-bit address of the data register (0x00 ~ 0x7f)
Execution time: one instruction cycle
Execution Process: 0x00 → F
1 → Z
Status flag impact: Z
Note: The command is used to reset the data register, and the parallel position 0 indicates Z.
Command example: clrf trisb; all I/O pins of port B are set as output
Subwf subtract W register content from the data register content
Syntax: subwf F, d
Operand: F is the low 7-bit address of the data register (0x00 ~ 0x7f)
D is the low 7-bit address of the destination register (0x00 ~ 0x7f)
When d = F, the result is placed in the f data register, and the W register content remains unchanged.
When d = W, the result is placed in W register, and the data register F content remains unchanged.
Execution time: one instruction cycle
Execution Process: [f]-[w] → D
Status flag impact: Z DC C
Note: The w register is a subtrahend in this command.
When [f] = [w], the result of subtraction is 0, then z = 1
If [f]> [w] does not take place, c = 1
When [f] <[w], a bid occurs, c = 0
In fact, in the PIC single-chip microcomputer, this command is to obtain the complement code for the W register content and then add it to the subtrahend. Therefore, it is different from other single-chip microcomputer when determining whether there is a bid. Please note that
Command example:
Movlw 0x23; W = 0x23
Movwf TMP; TMP = 0x23
Movlw 0x32; W = 0x32
Subwf TMP, W; TMP-W: Save the result to W, W = 0xf1, TMP = 0x23
; Process: TMP = 0x23, W find the completion code is 0xcd, So 0x23 + 0xcd = 0xf1, And because TMP <W, c = 0