Extended ROM (oprom)

Extended ROM Base register This PCI register must be implemented if an extended ROM (oprom) is required to be embedded in the function card. Many PCI features are embedded in the device ROM, which contains the device driver for that feature. The starting memory address and size of the extended ROM are defined in the extended ROM base register and the extended ROM base register is in double word 12 in the configuration header area. As shown in Figure 1-1, the system must be automatically configured as soon as it is added so that each function's IO and memory decoder can identify mutually exclusive address ranges. Therefore, the configuration software must be able to detect how much storage space is required for an extended ROM. In addition, in order to establish its ROM position in a conflict-less address range, the system must be able to programmatically control the ROM's address decoder.

Figure 1-1 Extended ROM Base Register when the boot configuration program detects that a feature has implemented an extended ROM base register (usually writes "1" to it and reads it back), you must immediately check the first two locations of the ROM, check the signature of the extended ROM, and determine if the ROM is actually installed (that is, the ROM socket may be empty). If installed, the configuration program must map (Shadow) Rom and execute its initialization code. The format of the extended ROM base register is shown in Figure 1-1:

L bit 0 is 1, which means the ROM address decoder that enables the feature (assuming the storage space in the command register is also set to 1).

L bit [10:1] reserved.

L bit [31:11] is used to specify the starting address of the ROM (this address is divided according to the size of the ROM). For example, suppose that a programmer writes a 0xFFFFFFFE to an extended ROM base register (that is, to clear the 0-bit-extended ROM permission to prevent the ROM address decoder from being enabled before allocating the starting storage), then read the register, and the resulting value, if 0xfffe0000, illustrates the following issues:

The value of L-bit 0 is 0, which indicates that the ROM address decoder is currently disabled.

L bit [10:1] reserved.

L in the Base Address register field (that is, bit [31:11]), bit 17 is the least significant bit that the programmer can set to 1. The binary weight of the bit is 128K, which indicates that the ROM decoder needs to allocate 128K of storage space to ROM. The programmer then writes a 32-bit start address to the register, assigning the ROM start address to a 128KB address boundary. The storage space bit in the command register takes precedence over the extended ROM allowed bits. The extended ROM of this feature should respond to memory access only if the memory space bit (in its command register) and the extended ROM allow bits (in its extended ROM base register) to be set to 1 o'clock simultaneously.