FFT IP Core analysis of Quartus II and Modelsim-altera combined simulation FFT IP Core

FFT IP Core Features

Parameter settings

There are 4 modes of the FFT IP core, namely:

• Burst mode (Burst);
• Cache burst Mode (Buffered Burst);
• Flow mode (streaming);
• Variable flow mode (Variable streaming);

In the first 3 mode, the operation speed is increased, and the occupancy resource is incremented, and the 4th mode (Variable streaming) can be used to change the FFT size online. The speed and flow patterns are similar and the resources occupy more.

Divided into basic configuration and Advanced Configuration, the basic configuration includes the configuration of the FFT IP Core transformation length, FFT or IFFT, data mode, input, output order. Data accuracy and so on. The advanced configuration includes the structure of the FFT, the number of engines of the FFT.

Tansform:

Length: Is the transformation of the FFT, can only select the specified length, can not be customized.

Direction: Specifies whether the IP core completes an FFT transformation or a user-controllable FFT or ifft transformation.

/ o:

Data flow: Choose how you enter the data stream in 4 ways, Burst (Burst), Cache Burst (bufferedburst), stream mode (streaming), variable-length stream mode (Variable streaming), The first 3 ways to increase the speed of operation, the consumption of resources also increased in turn, the 4th way allows users to change the FFT of the transformation length, speed and flow mode (streaming) similar, but consumes more resources.

Input Otder: The order in which data is entered

Output order: The order in which the data is exported

Data and Twiddle:

Representation: The structure of data data, there are three types are:

• Block Floating (blocks floating point);
• Fixed point (fixed points);
• Single floating point (one float);

The Fixed point and single floating point can only be used in variable-flow mode (Variable streaming) for burst (Burst), Cache burst (Buffered Burst), Flow mode (streaming) can only be used (block floating point) block floating in three ways. A block floating point is a common scaling factor in one frame of data, which also poses a problem when a single zoom factor is used to increase the decimal (smaller number) error when there is a large size in a frame of data.

• Fixed point: The position of the decimal point is determined;
• Floating point: The position of the decimal point is indeterminate, and the floating-point number is converted to a binary deposit criterion: 20.25, converted to binary and normalized: 10100.01=1.010001*2^4; 32-bit floating point representation [31] 1-bit notation [30-23]8 bit exponent [22-00]23 decimal: 0 00000100 00000000000000000010001
• Block floating point: a data block of data sharing an exponent. For example, a data block has 6 data, then open 7 space, the first six put the data, the latter one put the index, the exponent is the largest value in this data block after the normalized exponent, the remaining 5 numbers in this index to hold the binary number;

Data input width: input data width

Twiddle width: Data widths of rotation factors, data width of rotation factor cannot be greater than data width of input data

Data output width: Output data width, the FFT calculation result is the real and imaginary part of the output with the scaling factor (EXP), the scaling factor is a negative representation, the output data need to move left (increase), the right shift, the output of the real and imaginary parts, scaling factor are signed number, This should be noted.

Latency estimaters:

• Calculation: Calculated delay
• Throughput Latency: Processing delay

There are two options in the advanced settings, one is the structure of the selection operation, and the other is the number of engines that select the FFT.

There are two kinds of operation structure: single output and Qaud output (four outputs), single output One clock period calculates only one FFT butterfly operation, four outputs one period calculates 4 base 4 's butterfly operation.

The more engines the FFT has, the faster the computation and, of course, the more resources it consumes. The default is four output, an FFT engine, the default settings.

After setting the parameters, you can click Generate HDL to generate HDL files (synthetic files and simulation files).

Interface Signal Information

A clock, the clock is the FFT IP core operation of the clock;

A reset, Reset_n is the FFT IP core reset signal, the low level is valid, when the reset Sink_ready signal has been low (invalid);

A Fft/ifft control line, Inverser sets the FFT transformation or Ifft transform, low level represents the FFT, high level represents IFFT. A sink, a source.

Sink signal:

• Sink_valid: Input to FFT, input data valid signal, keep valid during input data;
• Sink_sop: Input to FFT, input data start signal, align with first data, just keep one clock cycle;
• Sink_eop: Input to the FFT, input data end signal, and the last data alignment, just maintain a clock cycle;
• Sink_ready: FFT output, input ready signal, this signal is high means can input transform data, otherwise do not input transform data;
• Sink_error: Input to FFT, input error signal, set 0;
• Sink_real: Input to FFT, input real signal;
• Sink_imag: Input to FFT, input imaginary part signal;

SOURCE signal:

• Source_valid:fft output, output effective signal, the FFT transformation is completed, the signal is high, start output data;
• Source_ready: input to FFT, output data ready signal, set 1 can;
• SOURCE_ERROR:FFT output, output error signal, if the input data format is wrong, do not perform FFT transform, and give the error value, according to the error value can view the manual, determine how the input data is wrong;
• Source_sop:fft output, the output data start signal, and the output of the first data alignment;
• Source_eop:fft output, the output data of the terminating signal, and the output of the last data alignment;
• Source_real:fft output, the real part of the output data;
• Source_imag:fft output, the imaginary part of the output data;
• Source_exp:fft output, scaling factor of data;

Output Data format

Output range of the Source_exp

Note:

• FFT IP Core input data and output data, scaling factor are signed number;
• The result of the actual operation is the combination of the real part and the imaginary part and the scaling factor, if the scaling factor is negative, the real part and the imaginary part to move the corresponding number of digits, if it is a regular right shift, for example: The scale factor width is 6, the binary value is 101011, the value is signed number, represents-21, then the real and imaginary parts need to move left 21 bits is the final result;
• If FFT inverse transformation, only need to put inverser 1 can;

Burst interface Timing

Streaming interface Timing

The stream I/O data flow structure allows input data to be continuously processed and output continuous complex data streams. This process does not need to stop the FFT function data flow in and out.

Note: In each frame of data transmission should pay attention to sink_valide, sink_ready,inverse to synchronize with Sink_sop.

When the data conversion is completed, the FFT module will source_valid to be valid, and output the transform domain data in a natural order, and the FFT module output SOURCE_SOP represents the output of the first valid data. After n data (one frame) is transformed to the end of N-Clocks, the FFT module SOURCE_EOP the output data to the end of a valid representation. The output timing diagram is as follows.

The FFT gigabit function uses the Altera Atlantic Interface i/0 protocol, the input interface is the primary device sink (master Sink) and the output interface is the primary device source (master source).

After the reset signal is invalid, the data source will be sink_valide to high efficiency, to the FFT notification at the input of at least N complex data sample points can be entered. FFT functions set the sink_ready signal high to indicate the ability to receive these input signals. When the Sink_ready (FFT core emitted) and the sink_valide are active simultaneously, the transmission begins. The data source loads the first complex data sample into the FFT function, while the SINK_SOP (start) signal is placed high, indicating the start of the input module, the SINK_SOP signal is reset in the next clock cycle, and the data sample points are loaded in a natural order; When the last data is entered, SINK_ EOP is set to active, Sink_valid is still active, and the transfer of this frame data is complete. The Sink_sop is then set to valid on the next clock, and the previous procedure is repeated.

Sink_sop must be valid with Sink_valid and is a cycle, otherwise the source _error appears 01 error relative to Sink_valid lag, the search manual found that valid goes high, but there was no start of Frame How many cycles are sink_sop lag 01.

FFT IP Core analysis of Quartus II and Modelsim-altera combined simulation FFT IP Core