Fgpa Reset [Turn]

About the reset of the Fgpa

When I started to learn FPGA, always puzzled: FPGA is not no reset discipline, but always see a reset signal. Where does this reset signal (which we call rst_n) come from?

In fact, it can be obtained from two aspects, just like our MCU.

1. Power-on automatic reset
2. Manual key Reset

Considering the initialization of the system may take a certain amount of time, need to write a section of Verilog code to delay the reset, the code is integrated is the process of automatic reset, power-on automatic reset to the external hardware to provide a low-level pulse, the second method requires a key reset key circuit. As a normal system, the power-on automatic reset and the manual key reset are all necessary, and the two are actually inseparable.

Power-on automatic reset

The principle is very simple, write a reset module, waiting for a stable time, the reset signal to pull down a long enough time, and then pull the reset signal high.

The following Verilog source code, external key reset will also act as a pin input for the module, for the global reset operation of the asynchronous, the normal reset operation to be carried out, must require the external has a short pulse action on the rst_n signal, which can be achieved by the RC circuit in the key circuit.

1 /**************************************2 * Function: Power-on reset module3 * Input Parameters:4 * clk:50m Clock input5 * Rst_n: External key global reset signal6 * Output Parameters:7 * Sys_rst_n: System global sync reset signal8 ***************************************/9 ModuleResetTen ( One     inputCLK, A     inputRst_n, -     OutputSys_rst_n - ); the  - //------------------------------------------ - //Delay 100ms for steady state - Reg[ A:0] CNT; +  always@(PosedgeAlor Negedgerst_n) - begin +     if(!rst_n) ACNT <=0; at     Else -         begin -         if(CNT < at'd50_00000)//100ms -CNT <= cnt+1'B1; -         Else -CNT <=CNT; in         End - End to  + //------------------------------------------ - //Rst_n synchronism the Regrst_nr0; * Regrst_nr1; $  always@(PosedgeAlor Negedgerst_n)Panax Notoginseng begin -     if(!rst_n) the         begin +Rst_nr0 <=0; ARST_NR1 <=0; the         End +     Else if(CNT = = at'd50_00000) -         begin $Rst_nr0 <=1; $RST_NR1 <=rst_nr0; -         End -     Else the         begin -Rst_nr0 <=0;WuyiRST_NR1 <=0; the         End - End Wu  - AssignSys_rst_n =rst_nr1; About  $ Endmodule

Key manual Reset Circuit

The reference low-level circuit that does not use a dedicated chip is as follows:

One end of the reset pin in the circuit is connected to a common general purpose pin of the FPGA, so that the RC circuit in the circuit will generate the Rst_n low pulse in the above Verilog code, this is the beginning of this article says that the automatic power-on reset and the hardware key reset complement each other.

Please note that the value of two resistors, R21 if the R22 of two orders of magnitude above, so as to ensure that the key press is recognized as low level.

In the process of manual reset to ensure the stability of the key reset, you can also modify the above Verilog code for key suppression detection. Here is the waveform that catches the button when it is closed:

The keys can reach low levels within a few us, and the contact jitter is severe during this period.

1 ModuleRMV_BJ (2BJ_CLK,//acquisition Clock, 40Hz3RESET,//System Reset Signal4Button_in,//key input Signal5Button_out//output signal after shake-out6 );7 inputB_CLK;8 inputRESET;9 inputbutton_in;Ten Outputbutton_out; One Regbutton_in_q, button_in_2q, button_in_3q; A  -  always@(PosedgeBj_clkor NegedgeRESET) - begin the     if(~RESET) -     begin -Button_in_q <=1'B1; -button_in_2q <=1'B1; +button_in_3q <=1'B1; -     End +     Else A     begin atButton_in_q <=button_in; -button_in_2q <=button_in_q; -button_in_3q <=button_in_2q; -     End - End -  in  WireButton_out = button_in_2q |button_in_3q; -  to Endmodule

The above method does not produce a clock pulse signal, such as the next can be sampled with 10ms, while the key action will produce a clock pulse signal, easy to follow-up operation

1 /*--------------------------------------------------------------------------------------2 --FILENAME:DEBOUNCE_MODULE.V3 --Author:tony-ning4 --description: button Shake5 --called By:top module6 --Revision history:15-10-167 --Revision 1.08 --Company:9 --Copyright (c) all right ReservedTen ---------------------------------------------------------------------------------------*/ One  A  - ModuleDebounce_module - ( theClass//acquisition Clock, 40Hz -RSTN,//System Reset Signal -Button_in,//key input Signal -Button_out//output signal after shake-out + ); -     inputCLK; +     inputrstn; A     inputbutton_in; at     Outputbutton_out; -  -     Regkey_reg1,key_reg2,key_out; -     Reg[ -:0]count2; -      -      always@(PosedgeCLK)//CLK 25M in         begin -count2<=count2+1; to             if(count2==250000) +             begin -key_reg1<=button_in; thecount2<=0; *             End $key_reg2<=KEY_REG1;Panax Notoginsengkey_out<=key_reg2& (!KEY_REG1);  -         End the  +     AssignButton_out =key_out; A      the Endmodule

In addition to the above simple reset circuit, you can also use CAT811/TPS3823-33 and other special reset chip, you can eliminate the key button to shake the operation.

Fgpa Reset [Turn]