Fifth chapter combinational Logic circuit design

Fifth chapter combinational Logic circuit design

5.1-Gate Circuit

5.2 Encoder

5.3 Priority Encoder

5.4 Decoder

5.5 Multi-Channel Selector

5.6 Numeric Comparator

5.7 Addition device

In the previous chapters, we introduced VHDL language statements, grammar and the use of VHDL language design hardware circuit basic method, this chapter focuses on the use of VHDL language design of the basic combination of logic module method.

5.1-Gate Circuit

Two-input XOR gate

The logical expression for the two-input XOR gate is as follows:

The logical symbols of the two input XOR gates are shown in the figure, and the truth tables are shown in the following table:

A b y

0 0 0

0 1 1

1 0 1

1 1 0

Example: An XOR gate designed by means of behavior description

(based on logical expression)

LIBRARY IEEE;

Use IEEE. Std_logic_1164.all;

ENTITY XOR2_V1 is

PORT (A,b:in std_logic;

Y:out std_logic);

END XOR2_V1;

ARCHITECTURE behave of XOR2_V1 is

BEGIN

Y <= a XOR b; --Parallel statements

END behave;

Example: An XOR gate designed by means of data flow description

(According to the truth table)

LIBRARY IEEE;

Use IEEE. Std_logic_1164.all;

ENTITY Xor2_v2 is

PORT (A,b:in std_logic;

Y:out std_logic);

END Xor2_v2;

ARCHITECTURE dataflow of XOR2_V2 is

BEGIN

PROCESS (A, B)

VARIABLE comb:std_logic_vector (1 Downto 0);

BEGIN

Comb: = A & B;

Case Comb is

                when