Flash operation of STM32

Speaking of STM32 's Flsah, our first reaction is to install the program, in fact, STM32 on-chip flash not only used to install the program, but also to install chip configuration, chip ID, bootstrap program and so on. Of course, flash can also be used to load data.
Collected some of their own information, the information is summarized, do not want to see can be directly transferred to the back to see how to operate on it.
Flash category
According to the use, the flash in the STM32 slice is divided into two parts: the main storage block and the information block. Primary storage blocks are used to store programs, and the programs we write are typically stored here.  The information block is divided into two parts: system memory, option byte. The system memory storage is used to store the Boot program (BootLoader) in the system memory bootstrap mode, which is executed by the program when the program is loaded using the ISP mode. This area is written to bootloader by the chip factory and then locked and the user cannot change the area. Option byte The configuration information of the memory chip and the protection information of the primary storage block.

Page of Flash
STM32 Flash main storage block by page organization, some products 1KB per page, and some products per page 2KB. The typical purpose of a page is to erase Flash by page. From this point of view, the page is a bit like a generic flash sector.
Classification of STM32 Products
STM32 according to the Flash main storage block capacity, different pages, system memory, divided into small capacity, medium capacity, large capacity, interconnected type, a total of four categories of products.
Small capacity product primary storage block 1-32KB, 1KB per page. System memory 2KB.
Medium capacity Product primary storage block 64-128kb, 1KB per page. System memory 2KB.
Large capacity product main storage block above 256KB, each page 2KB. System memory 2KB.
The main storage block of interconnected products is more than 256KB, 2KB per page. System memory 18KB.
For a specific product category, you can check the data sheet, or according to the following simple rules to differentiate:
Stm32f101xx, stm32f102xx, stm32f103xx products, according to their main storage block capacity, must be small capacity, medium capacity, large capacity of one of the products, stm32f105xx, stm32f107xx is connected products.
Interconnected products and other three categories of the difference is bootloader, small medium and large capacity products bootloader only 2KB, only through the USART1 ISP, and connected products bootloader 18KB, can be USAT1, 4, Can and many other ways to do ISP. The bootloader of small empty volume products and medium capacity products are the same as those of large capacity products.

About ISPs and IAP
The ISP (in system programming) is programmed on the target board to program the chip directly, typically requiring a bootstrap program (BootLoader) to execute. The ISP is also called ICP (in circuit programming), in circuit programming, on-line programming. IAP (in application programming) is programmed in the application, which means that the end product is programmed by the end user in the use of the user program, to achieve online upgrade. IAP requires that the program be divided into two parts: the boot program, the user program. The boot program is always the same. IAP is also called programming in the program. The difference between an ISP and an IAP is that the ISP is generally reprogramming the chip, using the bootstrap procedure of the Chip factory. IAP is only part of the update process, using an IAP boot program developed by the appliance factory. In general, ISPs are subject to more restrictions, and IAP is more easily manipulated because it is a self-developed program.

Fpec
Fpec (Flash program/erase controller Flash programming/Erase Controllers), STM32 Erase and program Flash via Fpec. The FPEC uses 7 registers to operate the flash memory:

The Fpec key Register (Flash_keyr) writes the key value to unlock.
The option byte key Register (Flash_optkeyr) writes the key value of the unlock option byte operation.
The Flash Control Register (FLASH_CR) selects and initiates the flash operation.
The Flash Status register (FLASH_SR) queries the flash operation status.
The Flash address register (FLASH_AR) stores the flash operation address.
The image of the primary data in the option byte Register (FLASH_OBR) option byte.
Write the Protection Register (FLASH_WRPR) option byte to write the image of the protected byte.

Key value
To enhance security, when doing something, you need to write a specific value to a location to verify that it is a safe operation, which is called a key value. There are three key values for Flash in STM32:
Rdprt key = 0x000000A5 for de-reading protection
KEY1 = 0x45670123 for unlocking the flash lock
KEY2 = 0xcdef89ab for unlocking the flash lock

Flash lock
In the FLASH_CR, there is a lock bit, the bit is 1 o'clock, cannot write FLASH_CR register, thus also cannot erase and program Flash, this is called flash lock.
When the lock bit is 1 o'clock, the flash lock is valid, and only after the Flash_keyr is written to KEY1, KEY2, the lock is zeroed out by the hardware, thereby unlocking the flash lock. When the lock bit is 1 o'clock, the
Flash_keyr any error write operation (the first time is not KEY1, or the second is not KEY2), will cause the flash lock completely locked, once the flash lock completely locked, before the next reset, can not be unlocked, only after the reset, the flash lock will revert to the general lock state.
After reset, the lock bit defaults to 1 and the flash lock is valid, at which point it can be unlocked. After unlocking, flash erasure programming can be done. At any time, you can lock the lock position by the software, software locking and Reset lock is the same, can be unlocked.

Erase of primary storage block
The primary storage block can be erased either by page or by the whole piece.

Page Erase
Any page of the primary storage block can be erased through the Fpec page erase feature. We recommend that you use the following steps for page wipe:
1. Check the BSY bit of the FLASH_SR register. To confirm that there are no other flash operations in progress. You must wait for the BSY bit to be 0 to continue the operation.
2. Set the per bit of the FLASH_CR register to 1. Select the page erase action.
3. Set the Flash_ar register to the address where you want to erase the page, and select the page you want to erase. The value of the Flash_ar in which page range represents which page to erase.
4. Set the STRT bit of the FLASH_CR register to 1 to initiate the erase operation.
5. Waiting for the BSY bit of the FLASH_SR register to become 0 indicates that the operation is complete.
6. Querying the EOP bit of the FLASH_SR register, EOP is 1 o'clock, indicating that the operation was successful.
7. Read the erased page and do the verification. All data bits are 1 after the wipe is finished.

Whole piece Erase
The entire erase function erases the entire primary storage block, and the information block is not affected by this operation. It is recommended to use the following steps for an entire wipe:
1. Check the BSY bit of the FLASH_SR register to confirm that there are no other flash operations in progress.
2. Set the MER bit of the FLASH_CR register to 1. Select the entire erase operation.
3. Set the STRT bit of the FLASH_CR register to 1. Initiates an entire erase operation.
4. Waiting for the BSY bit of the FLASH_SR register to become 0 indicates that the operation is complete.
5. Querying the EOP bit of the FLASH_SR register, EOP is 1 o'clock, indicating that the operation was successful.
6. Read all the pages and do the verification. All data bits are 1 after the wipe is finished.

Programming of the primary storage block
Programming the primary block can be written to 16 bits at a time. When the PG bit of the FLASH_CR register is 1 o'clock, writing a half word (16 bits) in a flash address will start a programming session, and any non-half-word data is written, Fpec will generate a bus error. During the programming process (BSY bit 1 o'clock), any read-write Flash operation will cause the CPU to pause until this flash programming is complete. We recommend that you use the following steps to compile the primary storage block:
1. Check the BSY bit of the FLASH_SR register to confirm that there are no other programming operations in progress.
2. Set the PG bit for the FLASH_CR register to 1. Select the programming action.
3. Writes the half word to be programmed at the specified address. Write directly with the pointer.
4. Waiting for the BSY bit of the FLASH_SR register to become 0 indicates that the operation is complete.
5. Querying the EOP bit of the FLASH_SR register, EOP is 1 o'clock, indicating that the operation was successful.
6. Read the address that was written and verify the data.

Some questions about the master memory block Erase programming operation
1. Why do I have to check whether the BSY bit is 0 each time.
Because the BSY bit is 1 o'clock, you cannot write to any fpec register, so you must wait until the BSY bit is 0 o'clock to perform the flash operation.
2. What happens if you program without erasing.
STM32 before performing a programmatic operation, the address to be programmed is checked for erasure, and if not, the pgerr bit of the FLASH_SR register is not programmed and is 1. The only exception is that when the data to be programmed is 0x0000, it is programmed even if it is not erased, because 0x0000 can be programmed correctly even if erased.
3. Why read the data and verify it after the operation.
STM32 in some special cases (for example, Fpec is locked), it is possible that the operation is not performed at all, and the operation is not determined by the register alone. So, on the safe side, all data checks are read after the operation.
4. The amount of time to wait for the BSY bit to be 1 is appropriate.
Please refer to the data in the STM32 firmware library.
5. Flash Programming Manual said Flash operation (erase or programming), must open the internal RC oscillator (HSI), is not sure to use his flash erase and programming operations.
In this regard, I understand that when doing flash operations, it is necessary to ensure that his is not shut down, but the operating system can still be the HSE clock. STM32 Reset, his default is open, as long as you do not actively shut down for the low power to turn it, what clock can be used for flash operation. The procedure I have compiled also validates this.

Option byte
The option byte is used to store the chip user's configuration information.
Currently, all stm32101xx, stm32102xx, stm32103xx, stm32105xx, stm32107xx products, option bytes are 16 bytes. But this 16 bytes, every two bytes constitute a positive objection, that is, byte 1 is the inverse code of byte 0, byte 3 is the inverse code of byte 2, ... , byte 15 is the inverse of byte 14, so the chip user only has to set 8 bytes, and the other 8 bytes system is automatically populated with anti-code. So, sometimes, it is said that the option byte of STM32 is 8 bytes, but it takes up 16 bytes of space. The 8-byte positive code of the option byte is summarized as follows:

RDP byte 0. Read protected bytes, storing read protection settings for the primary storage block.
USER byte 2. User bytes, configuring watchdog, shutdown, standby.
DATA0 byte 4. Data byte 0, which is freely used by the chip user.
Data1 byte 6. Data byte 1, which is freely used by the chip user.
WRP0 byte 8. Write protection byte 0, which stores write protection settings for the primary storage block.
WRP1 byte 10. Write protection byte 1, which stores write protection settings for the primary storage block.
WRP2 byte 12. Write protection byte 2, which stores write protection settings for the primary storage block.
WRP3 byte 14. Write protection byte 3, which stores write protection settings for the primary storage block.

Option byte write enable
In FLASH_CR, there is a optwre bit, which is 0 o'clock, which does not allow option byte operations (erase, program). This is referred to as option Byte write Enable. The option byte operation is only available if the bit is 1 o'clock. This bit cannot be set to software 1, but software can be zeroed. Option byte operations are allowed only if the hardware automatically flash_optkeyr to the location 1 after writing to the KEY1 and KEY2 in turn. This is called unlock (open) option byte write Enable. After the bit is 1, the write enable can be turned off by software zeroing. After the reset, the bit is 0. The error operation does not turn off write enable forever, and write enable can be turned on as long as the correct key sequence is written. When write enable is turned on, it opens again, without error, and remains open. Obviously, before the option byte operation, the option byte operation can be performed before the Flash lock is unlocked and the option byte write enable is turned on.

Option byte Erase
We recommend that you use the following steps to erase option bytes:
1. Check the BSY bit of the FLASH_SR register to confirm that there are no other flash operations in progress.
2. Unlocks the optwre bit of the FLASH_CR register. That is, turn on write enable.
3. Set the Opter bit of the FLASH_CR register to 1. Select the option byte erase operation.
4. Set the STRT bit of the FLASH_CR register to 1.
5. Waiting for the BSY bit of the FLASH_SR register to become 0 indicates that the operation is complete.
6. Querying the EOP bit of the FLASH_SR register, EOP is 1 o'clock, indicating that the operation was successful.
7. Read the option bytes and validate the data.
Since the option byte is only 16 bytes, the erase is the entire option byte erased.

Option byte programming
We recommend that you program the option bytes using the following steps:
1. Check the BSY bit of the FLASH_SR register to confirm that there are no other programming operations in progress.
2. Unlocks the optwre bit of the FLASH_CR register. That is, turn on write enable.
3. Set the OPTPG bit of the FLASH_CR register to 1. Select the programming action.
4. Writes the half word to be programmed to the specified address. Initiates a programmatic operation.
5. Waiting for the BSY bit of the FLASH_SR register to become 0 indicates that the operation is complete.
6. Querying the EOP bit of the FLASH_SR register, EOP is 1 o'clock, indicating that the operation was successful.
7. Reads the option bytes written and validates the data. When programming the option byte, Fpec uses the low byte in the half word and automatically calculates the high byte (the high byte is the low byte of the inverse code) and begins the programming operation, which guarantees that the option byte and its inverse code are always correct.

Protection of primary storage blocks
The data in the primary storage block can be read-protected and write-protected. Read protection is used to protect data from being read out illegally. Prevent program leaks.
Write protection is used to protect data from unauthorized rewriting and to enhance the robustness of the program.

Read protection
After the primary storage block starts read protection, it simply has the following characteristics:
1. Programs that start from the primary storage block can perform read operations on the entire primary storage block and do not allow the first 4KB of the primary storage block to be erased programmatically, and the area after 4KB can be erased for programmatic operation.
2. From the SRAM startup program, the main storage block can not read, page erase, programmatic operation, but the primary storage block of the whole slice erase operation.
3. The primary storage block cannot be accessed using the Debug interface. These features are sufficient to prevent the main memory data from being read out illegally and to ensure the normal operation of the program.
Read protection is turned off only if the value of the RDP option byte is the RDPRT key value, otherwise read protection is initiated. Therefore, the operation of the Erase option byte will initiate read protection of the primary storage block. If you want to turn off read protection, you must program the RDP option byte to the RDPRT key value. Also, if you program the option byte so that RDP is changed from a non-key value to a key value (that is, from protection to non-protection), STM32 will erase the entire primary storage block before programming RDP. When the chip is factory, RDP writes the RDPRT key value in advance, turning off write protection.

Write protection
STM32 primary storage blocks can be write-protected in a domain. If you attempt to erase or program a write-protected domain, a write-protection error flag is returned in the Flash status register (FLASH_SR). STM32 primary storage block each of the 4KB,WRP0-WRP3 option bytes in each domain corresponds to a field that has a bit of 0 o'clock, and write protection is valid. For products over 128KB, WRP3. 15 protects all domains from domain 31 and beyond. Obviously, erasing the option byte will cause write protection for the primary storage block.

Option byte and its register image
We know that the FPEC has two registers that store the image of the option byte. So what is the difference between an option byte ontology (in Flash) and an image (in a register)?
The body of the option byte is just a flash, and its function is simply to power down the memory option byte content, and what really works is the image in the register. That is, whether a configuration is effective, not looking at the ontology, but looking at the image. The image is loaded with the value of the body after reset, and thereafter, unless reset, the image will no longer change. Therefore, changing the data of the ontology will not take effect immediately, only after the reset is loaded into the image. One thing to note is that when you change the value of the ontology so that the primary block read protection becomes unprotected, the entire primary storage block is erased before the ontology is changed. This is the only action that can be triggered by changing the body. But even so, read protection will wait until after the reset, loaded into the image before it is released.

A few mistakes in the Chinese version of the Flash programming Manual (not necessarily, but not in my understanding)
1. In the option Byte programming section:
After unlocking the Fpec, you must write the KEY1 and KEY2 separately (see section 2.3.1) to the Flash_optkeyr register, and then set the FLASH_CR register to ' 1 ', which allows you to program the option byte
In fact, after the Flash_optkeyr is written to KEY1 and KEY2, the OPTWRE bit is set to 1 by the hardware instead of writing 1 with the software. This can also be verified in the following register description. 2. In the description of read protection:
The value of read protection is not understood. The correct should be that when RDP is rdprt the key value, read protection is removed when read protection is applied to other values.


Looked for a long, originally only a few sentences can be solved, of course, is not to consider other functions, just simple read and write operations.
Where the write operation is as follows:
Flash_unlock (); Unlocking Flash Programming Erase Controller
Flash_clearflag (flash_flag_bsy| flash_flag_eop| flash_flag_pgerr| FLASH_FLAG_WRPRTERR);//Clear Flag bit
/*********************************************************************************
Flash_flag_bsy Flash busy Flag bit
Flash_flag_eop Flash operation end Flag bit
Flash_flag_pgerr Flash write error flag bit
Flash_flag_wrprterr Flash page Write protection error mark Net
**********************************************************************************/
Flash_erasepage (FLASH_START_ADDR); Erase the specified Address page
Flash_programhalfword (flash_start_addr+ (addr+i) *2,dat); Start writing from the addr address of the specified page
Flash_clearflag (flash_flag_bsy| flash_flag_eop| flash_flag_pgerr| FLASH_FLAG_WRPRTERR);//Clear Flag bit
Flash_lock (); Lock Flash Programming Erase Controller

From the above can be seen in the basic order is: Unlock-"clear flag bit (can not)-" erase-"write half word-" clear sign (also can not)-"locked. Where FLASH_START_ADDR is the macro definition of 0x8000000+2048*255,0x8000000 is the starting address of Flash, 2048 is because I use a large-capacity chip, according to the previous note flash address can see the chip per page capacity of 2K, That is, 2048 bytes, 255 represents the last page of the chip, which is based on different chips. Writing from the back page prevents stored data from destroying the user program. Addr*2 is because each data occupies 2 bytes (half word), although the write is 1 bytes of data, but the programming is 2 bytes, that is, a byte of data will also occupy two byte address.

The read operation is as follows:
U16 value;
Value = * (u16*) (flash_start_addr+ (addr*2));//start reading from the ADDR address of the specified page