Floorplan_editor Study Record

The Floorplan Editor overview contains some pace, Floorplanner, and FPGA editor operation settings, mainly for pin designations, layout locales, and the 10.1 version primarily supports only V4/v5/spartan 3 a. As a graphical interactive application, process UCF files with features such as:

• View and edit I/o constraints, Common logic (BRAM, clock logic, etc.)
• View and create zone and location constraints for logic in your design
• Establish the resource demand in the design
• Establish the resource layout of the target device

Related documents and points

Input file

• NGD Designing localized Web table files
• UCF User Constraint Original file

Output file

• UCF based on the settings generated/modified constraint record file

Design Essentials

• Display and search for specific elements and integrate selected elements into the same set
• View the specified resource view, PIN graph, constraint disable
• DRC detection, viewing rule text description
• Include and display the fly line for user system constraints
• Layout settings (following the SSO rules, specifying the pins to facilitate the migration of different packages, specifying the use of differential I/O pairs, providing graphical timing information/clock domain/io domains)

Floorplan Editor interface operation

• Package View: Packaging types have Bg/pg/fg/pq/cs, different package types correspond to different pin space distributions and displays, constraints can be achieved by dragging the specified port to the diagram pin (I/o solid ring is specified, the hollow ring is available, the specific color square is a special port) , the mouse points to a specific port to see the name, type and bank information, any one view of the selection will affect all other display table box selection, right mouse to specify the front/back of the chip display, specify different bank display color/clock field display color; disable specified IO
• Floorplan View: You can drag multiple resources from the Grid List window/design target window to constrain the layout, display the spatial distribution effect of constraint design, include the grid representing Slice, IO, global cache, Bram and processor, and combine rectangles to achieve non-rectangular zone constraints/ Disabled (repeated designations change the use rights); Specify whether the fly line is open or not
• Design Objects list: A list of objects, such as logical components, contained in the design Ngd file, each containing many configurable item parameters. Mainly to filter, constrain, group, remove constraints and specify the operation of the UCF file, and so on, the differential pair IO in the P-type designation will make the N type automatically assigned, the group transfer is the whole

Column	Description	Column	Description
Name	Object Name	Slew	Conversion speed (Fast/slow)
Net Name	NET name for the attached IO	Diff Pair	Differential Pair Object Name
Type	Object type	LOC	Location information
IO Direction	Io direction, can be changed (input, output, inout, and undefined)	IOB Delay	IOB delay, including both, Ibuf, IFD, or NONE.
Diff Type	Differential types, P_type, N_type, and unknown	Rerun	Forces a specified partial implementation from the specified point layout
Bank	Bank dependent information	Preserve	Change information for controlling re-layout
IO Standard	IO Standard (LVTTL,GTL, LVCMOS25)	Symbol Count	Total number of objects in group
Vreff	Vref Requirements	Range	Slice available numbers in area constraints
Vcco	Vcco demand	Size	The amount of slices specified by the zone constraint
Drive	Driver specified MA	Constraints File	The corresponding UCF file for saving information
Termination	Pull/drop-down designation

• Comprehensive list of Web tables: Hierarchical display based on design structure, mainly used for quick find and constraint

Toolsets and shortcut keys

• Quick action: Mouse specified to display feature brief, status bar description details
• PIN legend: Includes information such as symbols and type descriptions
• Color selection: Specify the components in the device, and adjust their shading settings

Shortcut	Menu	Command
F1	Help	Help Topics
F2		Note Toggles edit mode on a particular cell
F3	Edit	Find Next
F5	View	Refresh
F6	View	Zoom Full View
F7	View	Zoom out
F8	View	Zoom in
F9	View	Zoom to Box
F11	View	To Selected
Del	Edit	Remove Constraint
Esc	Cancel operation
CTRL + N	File	New
Ctrl+o	File	Open
Ctrl+s	File	Save
Ctrl+p	File	Print
CTRL + Z	Edit	Undo
Ctrl+x	Edit	Cut
CTRL + C	Edit	Copy
CTRL + V	Edit	Paste
Ctrl+f	Edit	Find
Ctrl+g	Edit	Group
Alt+enter	Edit	Object Properties

• Right-click Options (different windows have different menus, feature brochures have lists ...) ）

Design process

• Design flow based on NGD files and existing UCF files (load file, UCF to NGD overlay constraint, constraint modification)

• Top-level HDL design constraints (specify top-level file, analysis record port information , constraint settings , constraint save )

Basic operations

• Open editor independently: (command line input pace; Select Load file/auto new; Integrated pre-constraint to specify device; open editor or PACE), standalone mode has limited function and cannot be implemented after layout function
• Activate Zone redundancy: Select Enable area group padding in floorplan view and make redundant scale settings
• Activate disable mode: Start Disable tool, select Disable Resource
• Activate selection mode: Start the Selection tool, select the selected Resource
• Drag-and-drop constraint settings: Left-click Selection and drag to place the specified position to implement constraints; Group selection and constraint colored change reminders
• Filtering Features: Design object list with filtered feature options for quick Find with four options (state/Type/function/name)
• Group and Cancel: Combine selected objects into the same group, or cancel the previously set grouping
• Package PIN View: Toggle Package View/invert/color callout/Remove constraint/save file
• Selection action: Select logical units, remove selected cells, set parameter details
• Parameter settings: color settings (IO Group, clock area, pin-to-logic delay time), Floorplan view window settings (fly-line switch, grid switch, zone constraint, zone redundancy constraint, small area constraint switch over minimum estimate), background color (selected based on IO Group/clock Region/ Pin to logical delay time/report format for background shading), Package view window (top/Bottom view)
• View Toggle: Toggle Selection Area Show/hide, layout view, and package view toggle
• Find elements: Set filter type, automatically select filter results, match all/any items, parameter settings (match attribute settings, match degree < number has greater/less than/equal/approximate, text has equal/include/case slightly >, filter mode), multiple settings
• Color Matching: Coloring of specified components in different windows

Background, PIN, and region settings

• Clock area display, differential pair, input delay, CLB/IOB zone clock resource, IO Group, fly line via edit option or view option, control of sites and tiles display by shortcut keys; Display specified object parameters
• Cancels or specifies (region/region Group/Logical unit location), assignment policy for selected groups of objects (from top/bottom/left/right progression, one-by-one, per-mode), drag-and-drop scenarios, view/move/zoom/Add/Remove zone constraints, pin constraints via group placement and cancellation/file editing ...
• Check SSO analysis (subtract output, change IO standard, lower drive value, choose lower conversion rate), DRC detection, enhanced pin-constrained portability (floorplan > Make Pin Compatible with), clock analysis (Floorplan > Run Clock Analysis)

Recommended Learning

Documentation Program: Xilinx ISE help/software Help/floorplan Editor Help

Floorplan_editor Study Record