2018-2019-1 20165329 summary of the fifth week of Information Security System Design Basics

2018-2019-1 20165329 summary of the fifth week of Information Security System Design Basics

Summary of teaching material learning content

 

1. Random Access to memory is divided:

• Static RAM (SRAM): Each bit is stored in a bistable memory unit, and each unit is implemented by a six transistor circuit.

 

• Dynamic RAM (Dram): each bit of storage is charged for a capacitor.

 

• Features: Due to the bistability of SRAM, as long as there is electricity, it will always maintain its value, even if there is interference, such as electronic noise, to disrupt the voltage, when interference is eliminated, the circuit can also be restored to a stable value.
Application: high-speed cache memory, that is, it can be on a CPU chip or under a chip.

The units in traditional DRAM chips are divided into D super units, each of which is composed of w dram units, that is, a D x w dram stores a total of DW bit information. The superunit is rented out by a rectangular matrix of column C in the r row.

2. the disk uses read/write headers to read and write the bits stored on the magnetic surface. Such a mechanical movement is called seek. The time required to move the drive arm is called the seek time.

• Disk structure:
  It consists of disks. Each disk has two sides or is called a surface. The surface is covered with magnetic recording materials. There is a spindle in the center of the disc that can be rotated, so that the disc rotates at a fixed rotation rate, usually 5400 ~ 15000 rpm)
  

 

• Disk capacity: the maximum number of BITs that can be recorded on a disk is called its maximum capacity/capacity.
• Disk capacity:
• -Record density: The number of BITs that can be placed in the segment of the track 1 inch.
• -Track density: the number of tracks that can exist within a 1 inch radius starting from the disc center.
• -Surface density: the product of record density and track density.
• Formula for Calculating disk capacity:

• The disk reads and writes data in blocks of the sector size. The access time to the sector consists of the track time, rotation time, and transfer time.

 

3. The seek time multiplied by 2 is a simple and reasonable method to estimate the disk access time.

4. A device can execute a level or write a bus transaction without CPU interference. This process is called direct memory access.

5. SSD is a flash-based storage technology. Reading SSD is faster than writing. Flash memory blocks will wear out, but the lifetime is still very long, because the "average wear" logic will erase the average distribution on all blocks to maximize the lifetime of each block.

6. Increasing the density is much easier than reducing the access time.

7. A well-written computer program often has a good locality, called the local principle, which is a permanent concept. Locality includes temporal locality and spatial locality. Variables in the loop body have either time limitations or spatial limitations. Generally, as the step size increases, the space limitations decrease.

8. Learning to judge the limitations of a program is an important foundation for writing efficient code.

9. Data is always replicated back and forth between layer K and layer k + 1 Based on the block size. The fast size of any pair of adjacent layers is fixed. The access time and block size of the lower-layer devices in the hierarchy are long. The process of overwriting an existing block is called replacing or expelling the block.

10. Concepts of cache hit and miss

11. Row replacement when the cache does not hit: it also adopts the Locality Principle, which minimizes the probability of referencing the replaced row in the near future.

12. High-speed cache Performance Measurement: no hit rate, hit rate, hit time, and no hit penalty.

High-speed cache storage

• High-speed cache is an array of High-speed cache groups. Its structure can be described using tuples (S, E, B, m:

 
S: In this arrayS = 2 ^ sHigh-speed cache Group E: each group contains e high-speed cache Row B: each row is composed of a B = 2 ^ B bytes of data block M: each memory address has m-bit, forming m = 2 ^ m different addresses
 

• In addition, there are tag bits and valid bits:

 
Valid bits: each row has a valid bits indicating whether the row contains meaningful information flag bits: t = m-(B + S, the unique identifier is the index bit of the block group stored in this cache row: s block offset bit: the structure of the B cache divides m addresses into T tags, S group index bit and B block offset bit.
 

 

2018-2019-1 20165329 summary of the fifth week of Information Security System Design Basics