80386 of interrupts and exceptions

80386 in addition to maintaining 8086/80386 of the relevant functions, but also enhanced interrupt processing capabilities, and introduced the concept of "exception." This article describes the 80386 mechanisms for interrupts and exceptions.

8086/8088 divides the interruption into the internal interrupt and the external interruption two main categories. To support features such as multitasking and virtual memory, 80386 calls external interrupts "interrupts", calling internal interrupts "exceptions." As with 8086/8088, 80386 typically responds to interrupts or exceptions between two directives. 80386 handle up to 256 kinds of interrupts or exceptions.

1. Interruption

For 80386, interrupts are caused by asynchronous external events. External events and interrupt responses are not related to the instructions being executed. Typically, interrupts are used to indicate that an I/O device has completed an operation. As with 8086/8088, 80386 have two pins intr and nmi accept an external interrupt request signal. Intr accept a masked interrupt request. NMI accept an unshielded interrupt request.     In 80386, the IF flag in the flag register eflags determines whether to mask a blocking interrupt request. The external hardware also gives a 8-bit interrupt vector to the processor while sending an interrupt request signal through the intr. The processor reads the interrupt vector number given by the external hardware in response to a masked interrupt request. The processor has no rules for this interrupt vector number. But in the specific microcomputer system, the system must be set up by the software and hardware, so that the given interrupt vector number is not only corresponding to the external interrupt source, but also avoid the occurrence of the interrupt vector number using conflict. The programmable interrupt controller chip 8259A can work with 80386, can provide the above interrupt vector number to the processor according to the setting, also can handle the interrupt request priority level.     Each 8259A chip can support 8-channel interrupt request signal, if using 9 8259A chips (a main slice, 8 from the slice), can enable 80386 to accept the interrupt request signal of up to 64 interrupt source on the single pin intr. The processor does not mask interrupt requests from NMI. The processor does not receive interrupt vector numbers from external hardware in response to NMI interrupts. As with 8086/8088, in 80386, the interrupt vector number corresponding to an unshielded interrupt is fixed to 2. In order to mask interrupted nesting, whenever a NMI interrupt is accepted, the processor shields the internal response nmi again, which is not finished until the interrupt return instruction Iret. Therefore, the NMI handler should end with the iret instruction.

2. Abnormal

The      exception is 80386 caused by an abnormal or illegal condition detected during the execution of the instruction. Exceptions are directly related to the instructions being executed. For example, when the division instruction is executed, the divisor equals 0. Again, when executing instructions, the privilege level is found to be incorrect. When these conditions occur, the instructions cannot be completed successfully. Soft interrupt directives "INT N" and "into" are also classified as exceptions rather than interrupts, because the execution of these directives produces an exception event.     80386 identifies a number of different categories of exceptions and gives each category a different interrupt vector number. After an exception occurs, the processor handles the exception as if it were in response to an interrupt. That is, according to the interrupt vector number, the corresponding interrupt handler is transferred. It may be more appropriate to refer to this interrupt handler as an exception handler.      classify exceptions further into faults (Fault), traps (trap), and Abort (Abort), depending on whether the program that caused the exception can be recovered and recovered. We refer to the corresponding exception handlers as fault handlers, trap handlers, and abort handlers, respectively.      failure is an exception that notifies the system of an exception before the instruction that caused it. 80386 The fault is considered to be excluded. When the control is transferred to the fault handler, the saved breakpoint CS and the value of the EIP point to the instruction that caused the failure. In this way, after the fault handler has eliminated the fault, the instructions that caused the failure just now can be iret when the execution returns to the program that caused the failure to continue executing. This is a rerun that requires no additional involvement of the operating system software. The discovery of a failure may also occur during instruction execution before the instruction begins to execute. If a failure is detected during instruction execution, abort the fault instruction and revert the operand of the instruction to the value before the instruction began executing. This guarantees that the failure instructions will be executed correctly. For example, during the execution of a single instruction, if the segment does not exist, then stop the execution of the instruction, and notify the system to produce a segment fault, the corresponding segment of the fault handler can be loaded by the method to remove the fault, after which the original instructions can be successfully executed, at least no segment does not exist fault.      Trap is an exception that notifies the system of unusual conditions after an instruction that causes an exception. When the control is transferred to the exception handler, the saved breakpoint CS and the value of the EIP point to the next instruction to be executed in the instruction that caused the trap. The next instruction to be executed is not necessarily the next one. Therefore, the trap handler does not always extrapolate the instructions that generate the exception based on the saved breakpoint. When you move to the trap handler, the command that caused the trap should be completed properly, and it may change the register or storage unit。 Soft interrupt directives, single step exceptions are examples of traps.      Abort is an exception to the notification system when a system is in serious condition. The instructions that caused the abort are not certain. When a abort is generated, the executing program cannot be resumed. After the system receives an abort, the handler will re-establish the various system tables and may restart the operating system. An example of a stop is a hardware failure and an illegal value or inconsistent value in the system table.

3. Priority level

During the execution of an instruction, when more than one interrupt or exception is detected, the system is notified in the priority level listed in the table below. The highest priority interrupt or exception is notified to the system, and other lower-priority exceptions are discarded, while higher-priority interrupts remain suspended.

80386 response Break/exception Priority of	Break/Exception type	Priority level
Debugging failures	Highest
Other faults	↓
Trap directives int N and into	↓
Debug traps	↓
NMI interrupted	↓
Intr interrupted	Minimum