8086 interrupt mechanism

Computers usually have many input and output devices that request processing machines when they need services. The processors provide services to these devices after receiving the requirements.

When a device sends a service request to the processor, the processor will turn to and execute the corresponding service program (Interrupt Service Program ISR) after executing the current command ), after the execution is complete, the processor returns to the program before the execution of Isr for further execution. This processing method is the method of interruption, and the request initiated by the device is called the interrupt request (IRQ ).

In a microprocessor, the programmable interrupt controller (PIC) manages interrupt requests in the system. It is connected to the interrupt request pin of the device to receive the interrupt request from the device. When the device needs service, it activates the interrupt request pin signal, after the PIC detects the signal, it sends an interrupt signal to the CPU. There are three situations:

1) PIC only receives one interrupt request signal, and the CPU does not execute the interrupt request at this time, the PIC sends the interrupt signal directly to the CPU.

2) If the PIC receives multiple interrupt request signals at the same time, but the CPU does not execute the interrupt request, the PIC compares the priority among the interrupt request signals and selects the highest priority to send the interrupt signal to the CPU.

3) When PIC receives multiple interrupt request signals and the CPU is executing the interrupt service program, the highest priority interrupt request signal selected by PIC is then compared with the interrupt service being executed, determine whether to send an interrupt signal to the CPU immediately based on the comparison result.

However, when PIC sends an interrupt signal to the int pin of the CPU, the CPU immediately stops and asks the PIC which interrupt service request to execute. The PIC sends the interrupt number corresponding to the interrupt request to the Data Bus to inform the CPU of the interrupted service program. The CPU queries the interrupt vector table by the interrupt number read on the Data Bus, obtains the address of the interrupt service program, and starts executing the interrupt service program, the processor then executes the interrupted program.

The above describes the interrupt handling process of the I/O device, which belongs to the category of hardware interruption. However, the interrupt is not only hardware, but can also be used for software, by using the int command and specifying the interrupt number using its operands, the CPU can execute the corresponding ISR.

 
Two 8259a chips can handle a total of 15-level interruptions. The Int pin of the chip is connected to the ir2 pin of the main chip, that is, the interrupt signal sent from the chip is used as the irq2 input signal of the main chip. The port address of the master chip is 0x20, and the base address of the slave chip is 0xa0, the role of the irq9 pin is the same as that of the irq2 of the PC/XT (PC/AT and PC/XT correspond to different data buses of the 8086 series, and PC/XT is an earlier model, 8-Bit Data Bus, 16-bit PC/AT Data Bus ), that is, the PC/at machine uses the hardware circuit to recharacterize the irq2 pin of the device using irq2 to the irq9 pin of the pic, and use the software in BIOS to redirect irq9 interrupt int 71 to irq2 interrupt int 0x0a, in this way, the eight-bit configuration card of the PC/XT using irq2 can still be used normally on the PC/AT machine, achieving backward compatibility.
Under the control of the bus controller, the chip has two states: programming status and operation status. The programming state is the state in which the CPU initializes the chip through the in and out commands. After the initialization program is completed, the chip enters the operating state. At this point, the chip can respond to the interrupt request (IRQ0-IRQ15) from external devices at any time ). The chip selects the highest priority interrupt request as the service object and sends an interrupt request to the CPU through the int pin of the CPU. After the CPU responds, the chip sends the interrupt Number of the corresponding interrupt request programmed from the Data Bus D7-D0, the CPU receives the interrupt number, find the interrupt vector table, and respond to the interrupt.

8086 interrupt Subsystem

8086 of the minicomputer systems use the 8259a Programmable Interrupt Controller Chip. Each chip can manage eight interrupt sources. Multiple interrupt vectors can be managed through multi-level connection. The PC/AT series uses two of the above chips, as shown in:

 

 

 

 

 

 

Interrupt vector table

The interrupt vector table is also called the Interrupt Descriptor Table. It is used to determine the physical address of the ISR corresponding to the interrupt through the interrupt number. 8086 the microcomputer supports 256 interrupts. In real mode, each interrupt vector is composed of four bytes, which indicate the segment value and offset of the interrupt service program, therefore, the entire interrupt vector table is 256*4 bytes = 1024 bytes. When the 8086 microcomputer is started, the program in the rom bios will initialize at 0x0000: 0x0000 of the physical memory and set the interrupt vector table. The default ISR of each interrupt is provided in the BIOS. The vectors in the interrupt vector table are arranged according to the interrupt number order. Therefore, given the interrupt number N, the corresponding physical address is: 0x0000: N * 4 (bytes ).
During BIOS initialization, 16 hardware interrupt vectors supported by the 8259a chip and the interrupt call Function Vectors provided by the BIOS with the interrupt number 0x10-0x1f are set. For vectors that are not actually used, enter the temporary address of the dumb interrupt service program. When the system boots and loads the operating system, the value of some interrupt vectors will be modified as needed.
For Linux operating systems, the display and disk read interruption functions provided by BIOS are required when loading the kernel. Before the kernel works properly. in the s program, reinitialize the 8259a chip and. in the s program, you can reset an interrupt vector table (that is, the Interrupt Descriptor) to completely discard the interrupt service function provided in the BIOS.
When the Intel CPU runs in 32-bit protection mode, the Interrupt Descriptor Table IDT must be used to manage the interrupt or exception. IDT is a substitute for the interrupt vector table. It acts like an interrupt vector. It only contains the address of the interrupt service program ISR and information about the privileged level and descriptor category.

Linux Kernel interrupt handling

For linux kernels, interrupt signals are divided into two types: hardware interrupt and software interrupt (abnormal), with a numerical sign between 0-, where int0-int31 (0x00-0x1f) each interrupted feature is set or retained by Intel, which is a software interruption (exception) that is caused by exceptions detected when the CPU executes commands. It can also be divided into fault and trap, interrupt int32-int255 (0x20-0xff) can be set by the user.
The interrupt int32-int47 corresponds to the IRQ0-IRQ15 of the hardware interrupt request signal from the 8259a interrupt control chip.
The system call interruption triggered by programming is set to int128 (0x80). The system call interruption is the only interface on which your program uses operating system resources.
During system initialization, the kernel first uses a "dummy interrupt vector (Interrupt Descriptor)" In head. s to set the default settings for all the 256 descriptors in the Interrupt Descriptor Table. This dummy interrupt vector executes a default "no interruptions" handler. When the program is executed due to an interruption, the message "unknown interrupt" is displayed )". The purpose of using the dummy interrupt vector is to prevent general protective errors.
The init/main. in the C program, reset these interrupt Descriptors (namely the interrupt vectors) to point them to the corresponding actual processing program. The initialization settings for the int0-int31 are usually reset in the traps. C program; the system call interrupts the int128 reset in the kernel/sched. C.
The Linux kernel uses two descriptors: interrupt gate and trap gate when setting IDT. The difference is the impact on the "interrupt permit flag" if in the flag register eflags. The if flag is reset when the interrupt gate is executed, which can prevent other interruptions from interfering with the processing of the current interrupt, the subsequent interrupt end command iret restores the original value of the IF flag from the stack, and the interruption of the execution of the trap gate does not affect the if flag.