Accelerator Conformance Interface

The accelerator conformance interface on the ZYNQ PS (Accelerator coherency Port, ACP) is a compatible AXI3 64-bit slave interface that connects to the SCU (Snoop Control Unit), providing the PL with asynchronous cache consistency for direct access to PS portals.

The processor can flag the transport on the ACP as either consistent or non-consistent. The Axi host on the PL side via arusers[1:0] Indicates whether the read transmission is consistent, via awusers[1:0] indicates the write transmission, and these signals are all AXI bus related signals. Cases where the device side or strongly requires sequential transmission are often treated in a non-consistent manner (these are the transmissions generated by the Axi host interface, which are not cached and often produce a fixed size and number of transmissions).

Introduction

The non-conforming transmission passes directly through the SCU, which appears in the Axi host interface unchanged.

The consistent transfer of the ACP slave to the Axi master becomes more or less transmitted, and some properties change.

When the ACP receives a consistent write request from an external host, the SCU checks the CPU core L1 the corresponding address in the data cache, and if hit, the consistency protocol empties and invalidate the corresponding cache row, merging the cleared data and writing requests.

When initiating a read request from an external host box consistent memory area, interact with the SCU, test whether the data is required to be stored in the processor L1 Cache, and if so, the SCU returns data directly to the requester, or if Miss,scu checks L2 Cache First, then accesses main memory.

"ACP request"

ACP consistency read request: when aruser[0] = = 1,arcache[1] ==1, while Arvalid is active, the ACP consistency read request is generated. At this point, the SCU enforces consistency.

When aruser[0] = = 0 or arcache[1] ==0, while Arvalid is active, the ACP non-conforming read request is generated. When the SCU does not enforce consistency, the read request is passed directly to the available SCU AXI master port to the L2 cache controller or OCM.

ACP conformance write Request: when awuser[0] = = 1 and awcache[1] = = 1, while Awvalid is valid, the ACP consistency write request is generated. The SCU enforces consistency when the data is present in a CORTEX-A9 processor, and the PS region logic first clears and invalidate the corresponding CPU data. When the data is not on either CPU, or when it has been cleared and invalidate, the write request is initiated through the Axi host interface of a CORTEX-A9 processor to L2 cache or main memory.

When awuser[0] ==0 or awcache[1] ==0, while Awvalid is active, the ACP non-conformance write request is generated. When the SCU does not enforce consistency, the write request is passed directly to an available SCU AXI master port.

"ACP restrictions"

Consistent access does not allow mutually exclusive accesses;

Consistent access does not allow lock-in accesses;

Write transmission, with length = 3, size = 3, write-through 11111111 will cause CPU cache line destruction;

Continuous access via ACP OCM may starve other axi hosts; limit burst size is less than 8 x 64bit characters.

"References"

Zynq-7000 EPP TRM (UG585)

The Effect and technique of System Coherence in arm multicore technology by John Goodacre, Senior program Manager, ARM Pro Cessor Division

ARM cortex-a9 MPCore TRM, section 2.4, Accelerator coherency Port

Accelerator Conformance Interface