ADC Configuration for STM32

This article has been presented to: http://bibber.blog.sohu.com/162815791.html

How many bits is the ADC?

12 Guests

How many ADCs are there?

One, 2 or more to 3, depending on the device, and each with multiple channels.

About the channel:

10.3.3 Channel Selection

There are 16 multichannel channels. Transformations can be divided into two groups: regular and injected. A series of transformations in any order on any number of channels constitutes a group conversion. For example, the conversion can be completed in the following order: Channel 3, Channel 8, Channel 2, Channel 2, Channel 0, Channel 2, Channel 2, channel 15.

Rule groups consist of up to 16 transformations. The rule channels and their conversion order are selected in the ADC_SQRX register. The total number of conversions in the rule group is written to the l[3:0] bit of the ADC_SQR1 register.

The injection group consists of up to 4 transformations. The injection channels and their conversion order are selected in the ADC_JSQR register. The total number of conversions in the injected group must be written to the l[1:0] bit of the ADC_JSQR register.

What is the difference between them:

Different groups save the data after the conversion is not the same place, the resulting interrupt flag is not the same.

In scan mode, the rule group has the ability to pass each channel data through DMA to SRAM, and the injected group data always exists in Adc_jdrx.

There are some other differences, not listed here.

Why this kind of design ad conversion, there must be a reason, but I do not know, therefore, I also have difficulty in understanding the various patterns of ad conversion. That is to say, for the understanding of knowledge, to put it in its application background to learn to learn well. As a result, the more relevant knowledge accumulates, the faster it learns, which is the so-called "foundation" problem. The depth of one's knowledge means that he is knowledgeable, has encountered many things, and can quickly find the "prototype" to deal with something. Of course, there are some people who have a very strong abstract learning ability, even if they can not find the "prototype", he will be able to learn very well. Basically, this kind of people's scientific literacy is higher, in engineers, engineering students are not rare.

Talk less, how do you use AD converters?

Take a source program as an example to read, and further understand the meaning of the symbol in STM32, I believe that later read Library source program, will be able to a higher level.

To see it clearly, the following code is in blue, while some of the code inserted in the comment for this code is indicated in red. The excerpt from the data sheet is indicated by a yellow bottom (the original data sheet excerpt is best with stickers, but the stickers are too painful to post, and a little lazy to steal).

/* ADC1 Start preparing configuration */

Adc_initstructure.adc_mode = adc_mode_independent;

/* Set ADC->CR1 19:16 to determine ADC operating mode, a total of 10 operating modes

#define Adc_mode_independent ((uint32_t) 0x00000000) 0000: Standalone Mode

#define Adc_mode_reginjecsimult ((uint32_t) 0x00010000) 0001: Mixed sync rule + injection sync mode

#define ADC_MODE_REGSIMULT_ALTERTRIG ((uint32_t) 0x00020000) 0010: Mixed sync rule + alternating trigger mode

#define ADC_MODE_INJECSIMULT_FASTINTERL ((uint32_t) 0x00030000) 0011: Mixed synchronous injection + fast alternating mode

#define ADC_MODE_INJECSIMULT_SLOWINTERL ((uint32_t) 0x00040000) 0100: Mixed synchronous injection + slow alternating mode

#define Adc_mode_injecsimult ((uint32_t) 0x00050000) 0101: Injection sync mode

#define Adc_mode_regsimult ((uint32_t) 0x00060000) 0110: Regular sync mode

#define ADC_MODE_FASTINTERL ((uint32_t) 0x00070000) 0111: Fast alternate mode

#define ADC_MODE_SLOWINTERL ((uint32_t) 0x00080000) 1000: Slow alternating mode

#define ADC_MODE_ALTERTRIG ((uint32_t) 0x00090000) 1001: Alternate trigger mode

*/

Adc_initstructure.adc_scanconvmode = ENABLE;

/* Adc_scanconvmode is defined in stm32f10x_adc.h as follows:

Functionalstate Adc_scanconvmode;

This parameter is used to specify whether the conversion is a scan (multi-channel mode) or a single conversion (single channel mode), which can be set to disable or enable.

In the data sheet, the scan bit is described in this way: scanning mode

This bit is set and cleared by software and is used to turn scan mode on or off. In scan mode, the channel selected by the ADC_SQRX or ADC_JSQRX register is converted.

0: Turn off scan mode

1: Using scan mode

Note: If the Eocie or Jeocie bits are set separately, the EOC or JEOC interrupts will occur only after the last channel has been converted.

In this way, if you need to convert multiple channels at once, this must be set to enable.

*/

Adc_initstructure.adc_continuousconvmode = ENABLE;

/* Functionalstate Adc_continuousconvmode;

This parameter is used to specify whether the conversion is continuous or single-time, and it can be set to enable or disable.

There are two parameters in the Functionalstate data type, then what is it, with F12 to touch melon, you can see its definition is as follows:

typedef enum {DISABLE = 0, ENABLE =! DISABLE} functionalstate;

So it's equivalent to being a bit variable, I understand, dispable=0 this no problem, enable=! Disable should be the exact 1?? Otherwise, the following settings will be problematic.

Using these two symbols to set the bits in the register, you also need to provide the location information, as shown in the following code:

TMPREG1 |= (uint32_t) (Adc_initstruct->adc_dataalign | Adc_initstruct->adc_externaltrigconv | ((uint32_t) Adc_initstruct->adc_continuousconvmode << 1));

This <<1 is the location information, Cont is the bit 1 of the CON2 register

By the way, there are a lot of such enum{} in the library definition, it is equivalent to a bit variable, when they are set, they themselves only provide 0 or 1, and to a certain one 1 or clear 0 of the operation, in the code must appear <<1 such format, And this 1 is the location information of one of the registers. In this way, when we look at the STM32 Library and data Sheet comparison, we can be more intuitive and more convenient.

Cont bit (bit 1) for setting CON2: Continuous Conversion

This bit is set and cleared by the software. If this bit is set, the conversion will continue until the bit is cleared.

0: One-time conversion Mode 1: Continuous conversion Mode

*/

Adc_initstructure.adc_externaltrigconv = Adc_externaltrigconv_none;

/* uint32_t Adc_externaltrigconv;

Define how to trigger the ad conversion, a total of 8 options, the following gives two to explain:

#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t) 0x00040000)

The 0x00040000 is written in binary, which is:

0000 0000 0000 0100 0000 0000 0000 0000

In contrast to the following instructions, it is not difficult to see, 19th: 17 bit is 010, that is, Timer 1 CC3 event triggered.

#define Adc_externaltrigconv_none ((uint32_t) 0x000e0000)

The 0x000e0000 is written in binary, which is:

0000 0000 0000 1110 0000 0000 0000 0000

In contrast to the following instructions, the Swstart method is to use the software flag to initiate the conversion.

Notes on extsel[2:0]:

Bit 19:17 extsel[2:0]: Select External event for start Rule Channel Group conversion

These bits select the external event that is used to start the Rule Channel Group conversion

The trigger configurations for ADC1 and ADC2 are as follows

000: Timer 1 CC1 event 100: Timer 3 Trgo Event

001: Timer 1 CC2 Event 101: Timer 4 CC4 Event

010: Timer 1 CC3 event 110:exti Line 11/tim8_trgo,

Only large capacity products with Tim8_trgo function

011: Timer 2 CC2 Event 111:swstart

The trigger configuration for ADC3 is as follows

000: Timer 3 CC1 event 100: Timer 8 Trgo Event

001: Timer 2 CC3 event 101: Timer 5 CC1 Event

010: Timer 1 CC3 Event 110: Timer 5 CC3 Event

011: Timer 8 CC1 Event 111:swstart

*/

Adc_initstructure.adc_dataalign = Adc_dataalign_right;

/*

This is used to set the data alignment mode, there are two possible:

#define Adc_dataalign_right ((uint32_t) 0x00000000)

#define ADC_DATAALIGN_LEFT ((uint32_t) 0x00000800)

Find instructions on the data sheet:

Bit 11:align: Data alignment

This bit is set and cleared by the software.

0: Right Justify 1: Align Left

*/

Adc_initstructure.adc_nbrofchannel = 1;

/* Adc_nbrofchannel is defined as follows:

uint8_t Adc_nbrofchannel;

Specify how many channels will be converted, the value of which can be 1~16, this data will affect the register ADC_SQR1, the following is the relevant code in STM32F10X_ADC.C:

......

TMPREG2 |= (uint8_t) (Adc_initstruct->adc_nbrofchannel-(uint8_t) 1);

TMPREG1 |= (uint32_t) tmpreg2 << 20;

ADCX->SQR1 = TMPREG1;

See MPREG1 |= (uint32_t) TMPREG2 << 20; In: 20, with the principle we have just understood above, the value of the low will be in the ADC_SQR1 20, and its value is 1~16, from the code can be seen here and minus 1, Then its set value is: 0~15, that is, 4bit is enough, then from 20 forward, that is, [23:20], then SQR1 in the use of what? Let's go to this clue and we'll find SQR1 in 23:20, see how it's used.

Bit 23:20 l[3:0]: Regular channel sequence length

These bits define the change in the rule channel

0000:1 Conversions

0001:2 Conversions

......

1111:16 Conversions

That is to set the conversion of several channels at once, it seems that our understanding is completely correct.

*/

Adc_init (ADC1, &adc_initstructure);

With the previous set of settings, you can finally execute the Adc_init function. After the execution is not enough, but also to specify the channel conversion sequence, sampling time, and then continue.

/* ADC1 Rule Channel (Channel15) configuration (see the beginning of the article for the Rule channel) */

Adc_regularchannelconfig (ADC1, adc_channel_15, 1, adc_sampletime_55cycles5);

/* This function has a total of 4 parameters, the first is a specified converter, depending on the device used, can be ADC1,ADC2,ADC3, the second parameter is the specified channel number, the third parameter is to specify the channel in the conversion sequence in the first few conversions, the fourth parameter is the specified conversion time

The first to second parameter is not difficult to understand, there is no more to say, take a look at the third parameter.

Let's take a look at the contents of this function, which is in STM32F10X_ADC.C, which is a function provided by the STM library:

void Adc_regularchannelconfig (adc_typedef* adcx, uint8_t adc_channel, uint8_t Rank, uint8_t adc_sampletime)

{     ...... The front is not written.

/* for Rank 1 to 6 */

if (Rank < 7)//This rand is the third parameter

{

/* Get the old register value */

TMPREG1 = adcx->sqr3;

/* Calculate The Mask to clear */

TMPREG2 = Sqr3_sq_set << (5 * (Rank-1));

The values of the SQR3 are as follows:

#define Sqr3_sq_set ((uint32_t) 0x0000001F)

Use 5 to multiply, please refer to stm32f10x data sheet: adc_sq3 in Sq1~sq6 each occupies 5 bits.

This understanding: If this rank is 1, then tmpreg2 this variable [4:0] The 5 bits will be 11111 (that is, the initial value of Sqr3_sq_set: 0x0000001f), if rank is 2, then tmpreg2 the variable's [9:5] will be 11111, i.e. TMPREG2 will be equal to: 0X000003E0, and so on.

/* Clear the old SQx bits for the selected rank */

TMPREG1 &= ~TMPREG2;

/* TMPREG2 reverse and, that is, clear out the corresponding 5 bits in the TMPREG1 * *

TMPREG2 = (uint32_t) Adc_channel << (5 * (Rank-1));

/* This time the TMPREG2 takes the channel value and then moves the same phase to the left by rank 5, 10, or more bits */

TMPREG1 |= TMPREG2;

/* Store the new register value */

ADCX->SQR3 = TMPREG1;

}

*/

The fourth parameter is the sample time setting, the code is as follows:

TMPREG2 = (uint32_t) adc_sampletime << (3 * adc_channel);

/* Set a new sampling time, why use 3, the reason is the same as above 5 */

TMPREG1 |= TMPREG2;

/* Store the new register value */

ADCX->SMPR2 = TMPREG1;

There are two things to do next, the first is to allow DMA transfer

/* Enable ADC1 DMA */

Adc_dmacmd (ADC1, ENABLE);

The second is to open the ADC1 to start the conversion.

/* Enable ADC1 */

Adc_cmd (ADC1, ENABLE);

These two things are not troublesome, so they are no longer analyzed.

This time the ADC conversion configuration is complete. Very troublesome ... Perhaps a powerful byproduct is trouble, no way.

ADC Configuration for STM32