ADC Verilog SPI Timing

I use the ADC081SD chip, Cpol:cs is pulled to low power sclk is high, Cpol for 1,cs was pulled to low power sclk for 0 o'clock, Cpol for 0;

The Cpha:cs is pulled to the low level after the first clock edge is 0, and the second clock along the acquisition data is 1.

When the corresponding acquisition data bits of the clock rise are stable, the rising edge is collected, and the clock falling along the corresponding acquisition data bits are collected along the falling edge.

As shown in the SCLK, the rising edge is stable, the falling edge data is unstable (then the clock drops along the data, rising along the data can be collected). Rising Edge Collection.

Module ADC
(
Input clk_in,//
Input rst_n_in,//
Input Adc_data,//caiji
Output REG CS,
Output Reg SCLK,
Output REG[7:0] Led

);

Generating status
REG[5:0] cnt=0;
[Email protected] (Posedge clk_in or Negedge rst_n_in)
Begin
if (!rst_n_in)
cnt<=0;
Else
Begin
if (cnt>=35) cnt<=0;
else cnt<=cnt+1;
End
End

Reg[15:0] data_reg=16 ' B0;

[Email protected] (Posedge clk_in or Negedge rst_n_in)
Begin
if (!rst_n_in) begin cs<=1;sclk<=1; End
Else
Begin
Case (CNT)
0:begin sclk<=1; cs<=1; End
1:begin cs<=0; End

2:begin Sclk<=0;end
3:begin sclk<=1;data_reg[15]<=adc_data;end//collected the highest bit of data Z2

4:begin Sclk<=0;end
5:begin sclk<=1;data_reg[14]<=adc_data;end//Data bits are collected z1

6:begin Sclk<=0;end
7:begin sclk<=1;data_reg[13]<=adc_data;end//collected the data z0

8:begin Sclk<=0;end
9:begin sclk<=1;data_reg[12]<=adc_data;end//collected the data DB7

10:begin Sclk<=0;end
11:begin sclk<=1;data_reg[11]<=adc_data;end//collected the data DB6

12:begin Sclk<=0;end
13:begin sclk<=1;data_reg[10]<=adc_data;end//collected the data DB5

14:begin Sclk<=0;end
15:begin sclk<=1;data_reg[9]<=adc_data;end//collected the data DB4

16:begin Sclk<=0;end
17:begin sclk<=1;data_reg[8]<=adc_data; end//captured the data DB3

18:begin sclk<=0;end////collected the DB2
19:begin sclk<=1; data_reg[7]<=adc_data; End

20:begin sclk<=0;end//
21:begin sclk<=1;data_reg[6]<=adc_data;end//collected the data DB1

22:begin sclk<=0;end//
23:begin sclk<=1;data_reg[5]<=adc_data;end//collected the data DB0

24:begin sclk<=0;end//
25:begin sclk<=1;data_reg[4]<=adc_data;end//captured Data Zero 4

26:begin sclk<=0;end//
27:begin sclk<=1;data_reg[3]<=adc_data;end//captured Data Zero 3

28:begin sclk<=0;end//
29:begin sclk<=1;data_reg[2]<=adc_data;end//captured Data Zero 2

30:begin sclk<=0;end//
31:begin sclk<=1;data_reg[1]<=adc_data;end//captured Data zero 1

32:begin sclk<=0;end//
33:begin sclk<=1;data_reg[0]<=adc_data;end//Captured data zero 0
34:begin cs<=1; led<=data_reg[12:5]; End//Data is latched, the LED's data will not jump when the next data is picked up
Endcase
End
End

Endmodule

ADC Verilog SPI Timing