ALTERA DE2 verilog HDL Learning Note 05-FPGA UART RS232

Design the simplest RS232 communication logic, the FPGA implementation will receive the data will be sent out, a total of two data transmission pins, a receive. Divide this communication module into three parts:

1. Baud Rate Control Module

2, send the module.

3. Receiving module

Here is the Code section:

<span style= "font-family:arial, Helvetica, Sans-serif;" >Baud_Counter.v</span>

Module Baud_counter (//Inputs input CLK, input reset, input reset_counters,//Outputs output reg baud_clock_rising_e

Dge, output reg Baud_clock_falling_edge, output reg all_bits_transmitted);
Parameter baud_counter_width = 9;
Parameter Baud_count = 5; Parameter Baud_tick_count = baud_count-1;
9 ' d433; Parameter Half_baud_tick_count = BAUD_COUNT/2;

9 ' d216;
Parameter data_width = 9;

Parameter Total_data_width = data_width + 2;
reg [(Baud_counter_width-1): 0] baud_counter;

reg [3:0] bit_counter;
	Control Baud_counter always @ (Posedge CLK) begin if (reset = = 1 ' B1) baud_counter <= {baud_counter_width{1 ' B0}};
	else if (reset_counters) baud_counter <= {baud_counter_width{1 ' B0}};
	else if (Baud_counter = = Baud_tick_count) baud_counter <= {baud_counter_width{1 ' B0}};
else Baud_counter <= Baud_counter + 1 ' B1; End/Control Baud_clock_rising_edge signal always @ (Posedge CLK) begin if (reset = = 1 ' B1) Baud_clock_rising_edge &lt
	; = 1 ' b0; else if (baud_Counter = = Baud_tick_count) Baud_clock_rising_edge <= 1 ' B1;
else Baud_clock_rising_edge <= 1 ' b0; End/Control Baud_clock_falling_edge signal always @ (Posedge CLK) begin if (reset = = 1 ' B1) Baud_clock_falling_edge &
	lt;= 1 ' B0;
	else if (Baud_counter = = half_baud_tick_count) Baud_clock_falling_edge <= 1 ' B1;
else Baud_clock_falling_edge <= 1 ' b0;
	End/Control bit counter always @ (Posedge CLK) begin if (reset = = 1 ' b1) bit_counter <= 4 ' H0;
	else if (reset_counters) bit_counter <= 4 ' H0;
	else if (Bit_counter = = total_data_width) bit_counter <= 4 ' H0;
else if (Baud_counter = = baud_tick_count) bit_counter <= bit_counter + 4 ' H1; End/Control all_bits_transmitted signal always @ (Posedge CLK) begin if (reset = = 1 ' b1) all_bits_transmitted <= 1
	' B0;
	else if (Bit_counter = = total_data_width) all_bits_transmitted <= 1 ' B1;
else all_bits_transmitted <= 1 ' b0;
 End Endmodule

Rs232_out.v

Module Rs232_out (//Inputs input CLK, input reset, input [data_width:1] transmit_data, input transmit_data_en,//OUTP

UTS output reg Serial_data_out, output reg Transmitting_data);
Parameter data_width = 8;

Parameter Baud_count = 9 ' d434;
Wire Shift_data_reg_en, read_input_en;
Wire Baud_clock;

Wire all_bits_transmitted;
Debug outputs//assign baud_clock = shift_data_reg_en;

Assign next_bit = data_out_shift_reg[0];

reg [data_width:0] Data_out_shift_reg;
	Initial begin serial_data_out <= 1 ' B1; Data_out_shift_reg <= {(data_width + 1) {1 ' b1}}; 
	All ones end @ (Posedge CLK) begin if (reset = = 1 ' b1) serial_data_out <= 1 ' B1; else serial_data_out <= data_out_shift_reg[0];
	Next bit end always @ (Posedge CLK) begin if (reset = = 1 ' b1) transmitting_data <= 1 ' b0;
	else if (all_bits_transmitted = = 1 ' b1) transmitting_data <= 1 ' b0;
else if (transmit_data_en) transmitting_data <= 1 ' B1;
	End always @ (Posedge CLK) begin if (reset = = 1 ' B1)	Data_out_shift_reg <= {(data_width + 1) {1 ' b1}};
	All ones else if (read_input_en) data_out_shift_reg <= {transmit_data,1 ' B0};
else if (shift_data_reg_en) data_out_shift_reg <= {1 ' B1, Data_out_shift_reg[data_width:1]};

End Assign read_input_en = ~transmitting_data & ~all_bits_transmitted & transmit_data_en; Baud_counter Out_counter (///Inputs. CLK (CLK),. Reset,. Reset_counters (~transmitting_data),//Outputs. Baud_
Clock_rising_edge (Shift_data_reg_en),. Baud_clock_falling_edge (),. all_bits_transmitted (all_bits_transmitted));

Defparam Out_counter.baud_count = baud_count, out_counter.data_width = data_width; /* Altera_up_sync_fifo Rs232_out_fifo (///Inputs. CLK (CLK),. Reset,. write_en (Transmit_data_en & ~fifo_is_full),. Write_data (Transmit_data),. Read_en (Read_fifo_en),//bidirectionals//Outputs. fifo_is_emp Ty (Fifo_is_empty),. Fifo_is_full (Fifo_is_full),. words_used (fifo_used),. Read_data (Data_FROM_FIFO)); Defparam Rs232_out_fifo. Data_width = Data_width, Rs232_out_fifo. Data_depth = Rs232_out_fifo.
Addr_width = 7;
 */Endmodule

Ra232_in.v

Module rs232_in (//Inputs input CLK, input reset, input serial_data_in, input receive_data_en,//Outputs output reg [(D

ATA_WIDTH-1): 0] received_data, output reg Receiving_data, output reg data_received, output baud_clock);
Parameter Baud_count = 9 ' d434;
Parameter data_width = 8;

Parameter Total_data_width = data_width + 2;
Wire shift_data_reg_en;


Wire all_bits_received;
Assign baud_clock = shift_data_reg_en;
reg [(Total_data_width-1): 0] Data_in_shift_reg;
Reg Receiving_data;



Reg Prev_receiving_data;
	Always @ (Posedge CLK) begin if (reset = = 1 ' b1) receiving_data <= 1 ' b0;
	else if (all_bits_received = = 1 ' b1) receiving_data <= 1 ' b0;
else if (serial_data_in = = 1 ' b0) receiving_data <= 1 ' B1;
	End always @ (Posedge CLK) begin Prev_receiving_data <= Receiving_data;
	if (Receiving_data==1 ' B1) data_received <= 1 ' b0;
		else if (prev_receiving_data==1 ' B1) begin data_received <= 1 ' B1;
	Received_data <= Data_in_shift_reg[data_width:1]; End End Always @ (Posedge CLK) begin if (reset = = 1 ' B1) data_in_shift_reg <= {total_data_width{1 ' B0}};
else if (shift_data_reg_en) Data_in_shift_reg <= {serial_data_in, data_in_shift_reg[(total_data_width-1): 1]}; End Baud_counter Rs232_in_counter (///Inputs. CLK (CLK),. Reset,. Reset_counters (~receiving_data),//Outputs. Bau
D_clock_rising_edge (),. Baud_clock_falling_edge (Shift_data_reg_en),. all_bits_transmitted (all_bits_received));
Defparam rs232_in_counter.baud_count= Baud_count, rs232_in_counter.data_width= data_width; /* Altera_up_sync_fifo Rs232_in_fifo (///Inputs. CLK (CLK),. Reset,. write_en (All_bits_received & 
	
	~fifo_is_full),. Write_data (data_in_shift_reg[(data_width + 1): 1]),. Read_en (Receive_data_en & ~fifo_is_empty), Bidirectionals//Outputs. Fifo_is_empty (Fifo_is_empty),. Fifo_is_full (Fifo_is_full),. words_used (Fifo_use
d),. Read_data (Received_data)); Defparam Rs232_in_fifo. Data_width = Data_width, RS232_in_fifo. Data_depth = Rs232_in_fifo.
Addr_width = 7;
 */Endmodule