ARMV7 LDR/STR Instruction Detailed

Because arm's arithmetic operations do not support the direct manipulation of memory addresses, the data in memory is loaded into the register first. The LDR directive is doing this, called the indirect access mode.

A total of 3 * 39 modes, First direct offset, first offset, then offset three categories, refers to how the operation of the source operand, is directly used, or before loading the operation of the source operand (such as address plus the number of values), or after loading the operand operation

Each big class is divided into three small categories, namely the source operand is an immediate number, register, or a scalar register (such as the number of registers to the left offset two bits, that is, by 4)

The assembly instructions and the corresponding C code are as follows

1ImmediateOffset:2 3LDR R0, [R1, #4]4R0 = r1[1];5 6Remember, again, the offset isinchBytes, so #4Would point to the second word (longint)inchOur array, thusinchC the array indice [1] would provide the correct data. 7 8RegisterOffset:9 Ten LDR R0, [R1, R2] OneR0 = R1[r2]; A  -Scaled RegisterOffset: -  theLDR R0, [R1, R2,LSL#4] -R0 = r1[(R2 <<4)]; -  -Immediate pre-Indexed: +  -LDR R0, [R1, #4]! +R1 + =4;r0 = *r1; A  atRegister pre-Indexed: -  - LDR R0, [R1, r2]! -R1 + = R2;r0 = *r1; -  -Scaled Register pre-Indexed: in  -LDR R0, [R1, R2,LSL#2]! toR1 + = (R2 << #2);r0 = *r1; +  -Immediate post-Indexed: the  *LDR R0, [R1], #4 $R0 = *r1;R1 + = 4;Panax Notoginseng  -Register post-Indexed: the  + LDR R0, [R1], R2 AR0 = *r1;R1 + = R2; the  +Scaled Register post-Indexed: -  $LDR R0, [R1, R2,LSL#2]! $R0 = *r1;R1 + = (R2 << #2);

The str instruction is to store the number in the register in memory, and the destination address is computed and manipulated in the same way as the source address in the LDR directive.

Immediate Offset:
LDR R0, [R1, #4] r0 = r1[1];
Remember, again, the offset is in bytes, so #4 would point to the second word (long int) in our array, thus in C the array Indice [1] would provide the correct data.
Register Offset:
LDR R0, [R1, R2] r0 = R1[R2];
Scaled Register offset:
LDR R0, [R1, R2, LSL #4] r0 = r1[(R2 << 4)];
Immediate pre-indexed:
LDR R0, [R1, #4]! R1 + = 4; R0 = *R1;
Register pre-indexed:
LDR R0, [R1, r2]! R1 + = R2; R0 = *R1;
Scaled register pre-indexed:
LDR R0, [R1, R2, LSL #2]! R1 + = (R2 << #2); R0 = *R1;
Immediate post-indexed:
LDR R0, [R1], #4] r0 = *R1; R1 + = 4;
Register post-indexed:
LDR R0, [R1], R2 r0 = *R1; R1 + = R2;
Scaled register post-indexed:
LDR R0, [R1, R2, LSL #2]! R0 = *R1; R1 + = (R2 << #2);

ARMV7 LDR/STR Instruction Detailed