ARMV8-A Series Study notes (9)--gic

When learning Mindshare armv8-a, there are several points:

First: Synchronous v Asynchronous

The features of the so-called Sync exception are:

1. Occurs when executing a specific instruction (such as when executing the load/store instruction, the corresponding virtual address is invalid, then an exception is generated)

2. End of exception handling, return address, is the address of the instruction that generated the exception

3. The exception is accurate (precise)

The so-called async is an external event, such as an interrupt (interrupt)

Sync

1. Undefined exception (the corresponding opcode is invalid, or under the current El, there is no execution permission, two cases),

2. IL (one in pstate, Eret in the case of ... ）

3. The PC pointer is misaligned

The stack is misaligned

DATA ABORT (address not aligned)

4. Fall into a higher-level El (... ）

5. I&d aborts (ADDRESS translation)

6. SYSTEM Call (SVC, HVC, SMC)

7. Debug exception

8. Floating point exception,

Async

1. Physical interrupts (serror, IRQ, Fiq)

2. Virtual interrupts (Vserror, VIRQ, Vfiq?)  ? ?)

Second: precise v imprecise

The characteristics of the so-called precise exception are:

When an exception is generated, its corresponding instruction

All instructions prior to the instruction have been executed by PE,

All instructions after the instruction, including the instruction, are not executed by PE,

If there is a definite partition, then the exception is returned with a definite return address

Otherwise, it is imprecise exception, which causes the exception to be processed and does not know which address is the correct return address and executes from the new start

Irq,fiq, all sync is precise.

Serror and Async abort for imprecise

Third: Single-copy Atomic v multiple-copy Atomic (... ）