ARMV8 memory management architecture. Learning Notes

Directory

The 1th chapter is the hierarchical storage architecture. 2

1.1 Basic knowledge ... 2

1.1.1 from the data path description. 2

The 1.1.2 is described from the Data Interchange unit. 2

1.1.3 Cache data consistency topology. 3

1.2 System-level memory model ... 3

1.2.1 Memory properties. 3

1.2.2 Address space. 4

1.2.3-byte encoding support. 4

Chapter 2nd Virtual Memory System Architecture (VMSA) 5

2.1 vmsav8-64. 5

2.1.1 Address translation system. 5

2.1.2 The granularity of memory conversion. 6

2.1.3 Address Translation Stage 8

2.1.4 Description Format (descriptor format) 9

The 2.1.5 Descriptor memory property. 11

2.2 vmsav8-32. 11

2.2.1 Address Translation system. 11

2.2.2 Conversion table support. 12

2.2.3 Descriptor format. 12

The 2.2.4 Descriptor memory property. 13

2.3 TTW (address translation process). 14

2.3.1 Vmsav8-64 14

2.3.2 Vmsav8-32 16

3rd Chapter MMU Fault 19

3.1 Fault Type ... 19

3.2 Kernel How to handle reading null pointers. ... 19

What happened to 3.2.1 arm. 19

3.2.1 Kernel How to handle: 20

4th Chapter Vmalloc 22

4.1 Introduction ... 22

4.2 Basic Flow ... 22

4.3 Code Implementation Analysis ... 23

The 5th chapter is the Linux virtual memory layout. 27

5.1 User Memory Layout ... 27

5.1.1 Mem Mapping Memory allocation method (64-bit) 28

5.2 Kernel Memory Layout ... 29

5.2.1 ARM64 kernel memory layout. 29

5.3 Each memory domain and physical memory mapping relationship ... 31

1th Chapter Tiered Storage Architecture 1.1 Basic Knowledge

Generally, in order to ensure the overall performance of the computer, the communication between the memory and the CPU needs to ensure a high transfer rate, however this is limited to the size of the memory and expensive hardware implementation, the relationship between the transfer rate and memory capacity size follows the "Smaller is faster" principle, Using higher-capacity memory is bound to increase transmission latency and reduce performance. To optimize the overall performance of the computer, the ARMV8 storage System provides a balance between the amount of memory capacity and the latency of the transmission in a multi-level cache. A typical tiered storage architecture can be described in the following two ways. 1.1.1 from Data path description

。 PE issues Virtual address VA conversion requirements

。 Virtual Address VA is an attempt to obtain a physical address PA through the TTW mechanism of addressing translation.

。 The physical address PA may be in Level1 cache, Level2 cache, or main Memroy.

。 If the PA is neither in the cache nor in main Memroy, the page fault will appear and then reloaded by the OS implementation.

。 If the PA is found successfully, return to PE to continue execution.

1.1.2 from Data Interchange Unit description

Register  <=> Cache	Program ape/Compiler
Cache <=> main Memroy	cache  controller, implemented by HW