[ASIC] Data Synchronization

Data synchronization with same-frequency/different Phase Clock domains

When data was transferred from one clock domain to another clock domain, and the the and the clock domains be at the same clock-fr Equency, and is different clock phase for the both clock domain has different clock tree as show below.

From the figure, there is several important points to be highlighted.

2. The both clock domain's clock tree should be the same source;
1. Same PLL ' s output;
2. Different PLL, but same clock reference;
4. If d is multi-bits data, D should was better registered-output from clock domain-1 (thus it was easier for backend To balance the timing of d2[] and d3[] by adding less buffers);
2. From experience, there was no must-to-have such requirement if D1 and D4 are nearer in the floorplan of the DES Ign
4. If there is registers for d2[] and then the clock domain can has a long distance location, thus the clock tree For the both clock domain would have a clean boundary for dynamic clock management and without introducing much power O F buffers for Clock-tree ' s balance.
6. Between d2[] and d3[], balance buffer is added to meet the timing requirement for clock-2;

This method was benefit area comparing to A-SYNC-FIFO (the depth should being larger than 8) strategy for both 1-bit and multi -bits width data-synchronization. But the synthesis constraint should is put to the top-level of the 2 clock domains; And timing analysis should is very focus on this.

[ASIC] Data Synchronization