Avalon Slave Peripherals Simple Implementation--DE1-SOC Learning notes (2)

In the previous article has compiled a number of cyclone-v and avalon-mm information, in this article to a slave device simple implementation of the--7 segment of the digital tube implementation.

First a general sequence diagram of the avalon-mm:

first, the hardware design IP Logic implementation:

as the slave of the Avalon Bus, both the control signal and the address signal are input, and there is also a chipslect signal. When a device sends a READ/WRITE request to the device, the chipslect signal is valid, while the addres is the register address from the device. For example, if the device has a base address of 0x0100 and there are two 32-bit registers, the Chipselect is valid when a primary device is issued 0x0104 the device is selected, and the address received from the device is 1 (in this case, in words).

7 Segment Digital Controller is a write-only device, so only need clk,chipselect,address,write, and writedata signal can be. The SystemVerilog implementation logic is as follows:

//seg7.svModuleBcd2seg (inputLogic [3:0] Din,OutputLogic [7:0] dout); Always_combbegin     Case(DIN)'b0000:dout<='b100_0000; 'b0001:dout<='b111_1001; 'b0010:dout<='b111_1001; 'b0011:dout<='b011_0000; 'b0100:dout<='b001_1001; 'b0101:dout<='b010_0010; 'b0110:dout<='b000_0010; 'b0111:dout<='b111_1000; 'b1000:dout<='b000_0000; 'b1001:dout<='b001_0000; default:d out<='b111_1111;    Endcase   End Endmodule   ModuleSeg7_disp # (parametern=6)(inputLogic Clk,reset,chipselect,inputLogic [3:0]byteenable,inputLogic Write,inputLogic [ to:0] WriteData,OutputLogic [ -:0] segout); //assert (n<=8);Logic [N-1:0][3:0] Bcdcon;//To decoder Genvari;Generate      for(i=0; i<n;i++)        begin: Gen1 bcd2seg UI (. DIN (bcdcon[i][3:0]),. Dout (segout[i*8+7:8*i])); End endgenerate   always@(PosedgeCLK)begin    if(reset) Bcdcon<=0; if(chipselect=='B1)        begin        if(write) Bcdcon<=WriteData; End End  Endmodule

Avalon bus IP encapsulation    1) Open Qsys, select new Component New user device (IP Core) in IP Catalog, edit the necessary information and select the file, Analyze

2) Edit the Signals and Interfaces tabs, select the corresponding signaltype according to the function of the module signal, set Clock.reset on the Interfaces tab, and parameter of the Avalon signal

Note: Here the difference between words and symbol

3) Complete the edit, save the System build 1) Add the custom IP Seg7 to the Qsys, connect to the H2f_lw_axi_master interface of the HPS, assign base Address

2) Generate HDL, return to Quartus II 3) Connect external signal 4) Compile II) software design

Avalon Slave Peripherals Simple Implementation--DE1-SOC Learning notes (2)