Bootloader source code

Include "def. H"
# Include "2440addr. H"
# Include "2440lib. H"

# Define puts uart_printf
# Define printf uart_printf
# Define getch uart_getch

# Ifndef debug_version
# Define use_uart_int
# Endif

Extern u32 downloadaddress, downloadfilesize;
Static u8 * temp;

# Ifdef use_uart_int
Static void _ IRQ uart0rxint (void)
{
Clearsubpending (bit_sub_rxd0); // rsubsrcpnd = bit_sub_rxd0; // clear pending bit (requested)
Clearpending (bit_uart0 );

* Temp ++ = rdurxh0 ();
}

Static void _ IRQ uart1rxint (void)
{
Clearsubpending (bit_sub_rxd1); // rsubsrcpnd = bit_sub_rxd1; // clear pending bit (requested)
Clearpending (bit_uart1 );

* Temp ++ = rdurxh1 ();
}
# Endif

Void call_linux (u32 A0, u32 A1, u32 A2 );

Void comdownload (void)
{
U32 size;
U8 * Buf;
2010checksum;
Int up;
 
Puts ("/Nnow download file from uart0. ../N ");
Downloadaddress = _ noncache_startaddress;
Buf = (u8 *) downloadaddress;
Temp = buf-4;
 
Uart_getkey ();

# Ifdef use_uart_int
Up = uart_select (-1); // get the Console Port
If (! Up ){
Pisr_uart0 = (u32) uart0rxint; // data Interruption During serial port reception
Clearsubpending (bit_sub_rxd0 );
Clearpending (bit_uart0 );
Enablesubirq (bit_sub_rxd0 );
Enableirq (bit_uart0 );
} Else {
Pisr_uart1 = (u32) uart1rxint; // data Interruption During serial port reception
Clearsubpending (bit_sub_rxd1 );
Clearpending (bit_uart1 );
Enablesubirq (bit_sub_rxd1 );
Enableirq (bit_uart1 );
}
# Endif

While (u32) temp <(u32) BUF)
{
# Ifdef use_uart_int
Led_display (0 );
Delay (1000 );
Led_display (15 );
Delay (1000 );
# Else
* Temp ++ = uart_getch ();
# Endif
} // Length of the received file, 4 bytes
 
Size = * (u32 *) (buf-4 );
Downloadfilesize = size-6;

# Ifdef use_uart_int
Printf ("download file size = % d/N", size );
# Endif
 
While (u32) temp-(u32) BUF) <(size-4 ))
{
# Ifdef use_uart_int
Led_display (0 );
Delay (1000 );
Led_display (15 );
Delay (1000 );
# Else
* Temp ++ = uart_getch ();
# Endif
}

# Ifdef use_uart_int
If (! Up ){
Disablesubirq (bit_sub_rxd0 );
Disableirq (bit_uart0 );
} Else {
Disablesubirq (bit_sub_rxd1 );
Disableirq (bit_uart1 );
}
# Endif

# Ifndef use_uart_int
Printf ("download file size = % d/N", size );
# Endif
 
Checksum = 0;
For (size = 0; Size <downloadfilesize; size ++)
Checksum + = Buf [size];
If (checksum! = (BUF [size] | (BUF [size + 1] <8 ))){
Puts ("checksum fail! /N ");
Return;
}
 
Puts ("are you sure to run? [Y/n]/n ");
While (1)
{
U8 key = getch ();
If (Key = 'n ')
Return;
If (Key = 'y ')
Break;
}
 
Call_linux (0,193, downloadaddress );
}

 

# Include "def. H"
# Include "option. H"
# Include "2440addr. H"
# Include "2440lib. H"
# Include "2440slib. H"
# Include "MMU. H"

Void memorytest (void)
{
Int I;
U32 data;
Int memerror = 0;
U32 * PT;

//
// Memory Test
//
// Uart_printf ("Memory Test (% XH-% XH): WR", _ ram_startaddress, (_ isr_startaddress & 0xfff0000 ));
// Test SDRAM from _ ram_startaddress + 2 m
Uart_printf ("Memory Test (% XH-% XH): WR", _ ram_startaddress + 0x00200000, (_ isr_startaddress & 0xffff0000 ));

// Pt = (u32 *) _ ram_startaddress;
PT = (u32 *) (_ ram_startaddress + 0x00200000 );
While (u32) Pt <(_ isr_startaddress & 0xffff0000 ))
{
* PT = (u32) pt;
PT ++;
}
 
Uart_printf ("/B/BRD ");
// Pt = (u32 *) _ ram_startaddress;
PT = (u32 *) (_ ram_startaddress + 0x00200000 );
 
While (u32) Pt <(_ isr_startaddress & 0xffff0000 ))
{
Data = * PT;
If (Data! = (U32) pt)
{
Memerror = 1;
Uart_printf ("/B/bfail: 0x % x = 0x % x/N", I, data );
Break;
}
PT ++;
}
 
If (memerror = 0) uart_printf ("/B/bo. K./N ");
}

**************************************** **********************
Name: profile. c
Desc: To measuure the USB download speed, the wdt is used.
To measure up to large time, the wdt interrupt is used.
History:
S3c2400x profile. C is ported for S3C2410X.
**************************************** **********************/
# Include "def. H"
# Include "option. H"
# Include "2440addr. H"
# Include "2440lib. H"
# Include "2440slib. H"

# Include <stdarg. h>
# Include <string. h>
# Include <stdlib. h>
# Include <stdio. h>
# Include <ctype. h>

Static int intcount;

Void _ IRQ isrwatchdog (void );

Void timer_initex (void)
{
Intcount = 0;
Pisr_wdt_ac97 = (u32) isrwatchdog;
Clearpending (bit_wdt_ac97 );
Rsubsrcpnd = bit_sub_wdt;
Rintmsk & = ~ (Bit_wdt_ac97 );
Rintsubmsk & = ~ (Bit_sub_wdt );
}

Void timer_startex (void)
{
Int divider = 0;
Rwtcon = (pclk/1000000-1) <8) | (0 <3) | (1 <2); // 16us
Rwtdat = 0 xFFFF;
Rwtcnt = 0 xFFFF;

// 1/16/(65 + 1), interrupt enable, reset disable, watchdog enable
Rwtcon = (pclk/1000000-1) <8) | (0 <3) | (1 <2) | (0 <0) | (1 <5 );
}

 

Float timer_stopex (void)
{
Int count;
Rwtcon = (pclk/1000000-1) <8 );
Rintmsk | = bit_wdt_ac97;
Rintsubmsk | = bit_sub_wdt;
Count = (0xffff-rwtcnt) + (intcount * 0 xFFFF );
Return (float) count * (16e-6 ));
}

Void _ IRQ isrwatchdog (void)
{
Rintsubmsk | = bit_sub_wdt;
Rsrcpnd = bit_wdt_ac97; // clear pending bit
Rintpnd = bit_wdt_ac97;
Rintpnd; // prevent an double interrupt pending
Rsubsrcpnd = bit_sub_wdt;
Intcount ++;
Rintsubmsk & = ~ Bit_sub_wdt;
}

 

# Include "def. H"
# Include "option. H"
# Include "2440addr. H"
# Include "2440lib. H"
# Include "2440slib. H"
# Include "MMU. H"

// 1) only the section table is used.
// 2) The cachable/non-cachable area can be changed by mmt_default value.
// The section size is 1 MB.

 
Extern char _ ENTRY [];

Void mmu_init (void)
{
Int I, J;
// ============================ Important note ============ ====================
// The current stack and code area can't be re-mapped in this routine.
// If you want memory map mapped freely, your own sophiscated MMU
// Initialization code is needed.
// ================================================ ==================================

Mmu_disabledcache ();
Mmu_disableicache ();

// If write-back is used, the dcache shocould be cleared.
For (I = 0; I <64; I ++)
For (j = 0; j <8; j ++)
Mmu_cleaninvalidatedcacheindex (I <26) | (j <5 ));
Mmu_invalidateicache ();

# If 0
// To complete mmu_init () fast, icache may be turned on here.
Mmu_enableicache ();
# Endif

Mmu_disablemmu ();
Mmu_invalidatetlb ();

// Mmu_setmtt (INT vaddrstart, int vaddrend, int paddrstart, int ATTR)
// Mmu_setmtt (0x00000000, 0x07f00000, 0x00000000, rw_cnb); // bank0
If (rbwscon & 0x6) // Nor start
Mmu_setmtt (0x00000000, 0x07f00000, 0x00000000, rw_ncnb); // bank0
Else // NAND boot
Mmu_setmtt (0 x percentile, 0x00001000, (INT) _ entry, rw_cb); // bank0
// Maid (0x04000000, 0x07f00000, 0, rw_ncnb); // bank0
Mmu_setmtt (0x08000000, 0x0ff00000, 0x08000000, rw_ncnb); // bank1
Mmu_setmtt (0x10000000, 0x17f00000, 0x10000000, rw_ncnb); // bank2
Mmu_setmtt (0x18000000, 0x1ff00000, 0x18000000, rw_ncnb); // bank3
// Mmu_setmtt (0x20000000, 0x27f00000, 0x20000000, rw_cb); // bank4
Mmu_setmtt (0x20000000, 0x27f00000, 0x20000000, rw_ncnb); // bank4 for strata flash
Mmu_setmtt (0x28000000, 0x2ff00000, 0x28000000, rw_ncnb); // bank5
Mmu_setmtt (0x30000000,0x30100000,0x30000000, rw_cb); // bank6-1
Mmu_setmtt (0x30200000, 0x33e00000, 0x30200000, rw_ncnb); // bank6-2
//
Mmu_setmgr (0x33f00000, 0x33f00000, 0x33f00000, rw_cb); // bank6-3
Mmu_setmtt (0x38000000, 0x3ff00000, 0x38000000, rw_ncnb); // bank7

Mmu_setmtt (0x40000000, 0x47f00000, 0x40000000, rw_ncnb); // SFr
Mmu_setmtt (0x48000000, 0x5af00000, 0x48000000, rw_ncnb); // SFr
Mmu_setmtt (0x5b000000, 0x5b000000, 0x5b000000, rw_ncnb); // SFr
Mmu_setmtt (0x5b100000, 0xfff00000, 0x5b100000, rw_fault); // not used

Mmu_setttbase (_ mmutt_startaddress );
Mmu_setdomain (0x55555550 | domain1_attr | domain0_attr );
// Domain1: no_access, domain0, 2 ~ 15 = client (AP is checked)
Mmu_setprocessid (0x0 );
Mmu_enablealignfault ();

Mmu_enablemmu ();
Mmu_enableicache ();
Mmu_enabledcache (); // dcache shocould be turned on after MMU is turned on.
}

// ATTR = rw_cb, rw_cnb, rw_ncnb, rw_fault
Void changeromcachestatus (int attr)
{
Int I, J;
Mmu_disabledcache ();
Mmu_disableicache ();
// If write-back is used, the dcache shocould be cleared.
For (I = 0; I <64; I ++)
For (j = 0; j <8; j ++)
Mmu_cleaninvalidatedcacheindex (I <26) | (j <5 ));
Mmu_invalidateicache ();
Mmu_disablemmu ();
Mmu_invalidatetlb ();
Mmu_setmtt (0x00000000, 0x07f00000, 0x00000000, ATTR); // bank0
Mmu_setmtt (0x08000000, 0x0ff00000, 0x08000000, ATTR); // bank1
Mmu_enablemmu ();
Mmu_enableicache ();
Mmu_enabledcache ();
}

Void mmu_setmtt (INT vaddrstart, int vaddrend, int paddrstart, int ATTR)
{
Volatile u32 * PTT;
Volatile int I, nsec;
PTT = (u32 *) _ mmutt_startaddress + (vaddrstart> 20 );
Nsec = (vaddrend> 20)-(vaddrstart> 20 );
For (I = 0; I <= nsec; I ++) * PTT ++ = ATTR | (paddrstart> 20) + I) <20 );
}