Bus (b)

Bus Standard: It can be regarded as a standard interface between the system and each module, module and module.
There are currently the following types:

1.ISA, using a separate CPU bus clock, is IBM in order to adopt a full 16-bit CPU and launched. Thus the CPU can use a higher clock than the bus frequency, which is advantageous to the CPU performance improvement. There is no bus quorum, so multiple master systems are not supported, and the data transfer must be managed by the CPU or DMA interface, and the CPU spends a lot of time controlling the exchange of data with external devices.
2.VESA, local bus standard, outside the system for more than two modules to provide high-speed transmission of information channels. Through the local bus controller, the high-speed IO device is directly attached to the CPU, which realizes the exchange of the data between the CPU and the high-speed IO device.

3.EISA, extended on the ISA, support multiple mainline master, burst mode.
4.pci,gui the application of the multimedia technology of the graphical user interface, the Isa,eisa bus is limited by the bandwidth and cannot be adapted. The main features of PCI are as follows:
3.1, High performance

3.2, good compatibility

3.3, Plug and Play support

3.4, support multi-master device capability

3.5, processor and memory subsystem parallel operation

3.6, data and address parity

3.7, two voltage standards, 5v,3.5v

3.8, extensibility is good

3.9, good compatibility

3.1 Multiplexing

5.AGP, video card dedicated local bus.

6.RS232-C, serial communication standard. Coordination of the DTE,DCE

7.USB, peripheral quick Connect.

Bus structure:

1, single bus, at the same time, multiple devices are not allowed to transmit data to the bus. Easy to create bottlenecks.

2, multi-bus, the low-speed IO device from the single bus to separate. A portion of the functionality is given to the channel, which has the ability to control IO.

Different types of IO devices can also be categorized, which speeds up productivity

In the three bus, at any time can only use a bus, main memory bus, DMA bus, can not simultaneously access to main memory.

Another three-bus, four-bus

Bus control:

The device on the bus is divided into main equipment according to the control function, from the equipment. The master is provided with control, from which only the corresponding bus command is set. On the bus, the transmission of information is initiated by the main setting.

Bus award is divided into: centralized, distributed, the former control logic in one place, (CPU), the latter is divided into buses and other components and equipment.

Centralized arbitration:

1, chain-type query,

2, Counter timing query

3, independent request mode

The bus consent signal BG is serially routed from one IO interface to another IO interface, and if the interface has a BR bus request, BG will no longer pass it down. The interface obtains the bus use right and establishes a BS bus busy signal, which indicates that the bus is occupied. The closest to the bus control will be control first.

Features: Easy to expand, sensitive to circuit faults, low priority is difficult to obtain requests.

One less bus consent line BG, more than one set of device address lines. After the bus control unit is sent to the request by BR, the calculator in the bus control unit starts counting and sends a set of address signals to each device through the device address line when the bus is not used. When a request consumes the bus's device address in line with the count value, the bus access is obtained, at which point the Count query is terminated. The counter's initial value is variable, the circuit fault is not as chain-sensitive, but the control line is more complicated.

Each device has a pair of bus request lines BR and bus-line BG, to use the bus, the device is issued a request signal. There is a queuing circuit in the bus control unit that determines which device's request is based on the order of precedence.
Features: Fast response, flexible priority control, multiple control limits, and complex bus control.

Bus (b)