Clock setting for at91rm9200 startup

There are four clock sources in 9200:

Slow clock (SLK)

Main clock)

PLLA, pllb

There is a difference between the master clock and the host clock.

The main clock refers to the clock of the input main oscillator.

The host clock (mck) refers to the CPU clock frequency.

 

The host clock can be selected (the clock selector) as its own clock in four clock sources.

 

9200 clock changes after startup

Because the system enters the slow clock Status After resetting, the host clock source is provided by the slow clock. However, because the built-in boot program may have started, you need to reset the slow clock to the host clock source at startup. However, the host clock register requires that the written value cannot be directed to the current value. Therefore, the code is divided into two steps:

The loop is used to determine whether the clock is set successfully.

To reduce power consumption, You need to disable the PLL and the code is omitted.

After the preceding actions are completed, the system's host clock source is a slow clock. However, when the system is running normally, it is impossible to use a slow clock as the clock source (for example, PLLA is used as the clock source). Further settings are required.

For the PLL clock, its clock source is the master oscillator clock (that is, the main clock), so you must first open the master clock, the Code is as follows:

Then perform other initialization actions. Until running to 91f _ Lowlevelinit function.

Because the master clock is turned on before, but it is not determined whether the start is successful, so 91f _ Lowlevelinit first 91f The _ waitformainclockfrequency function checks whether the master clock is enabled. Code omitted

After the main clock is turned on, you can set the real PLL clock source. The main body of the Code is 91f _ Initclocks function.

Since the clock settings must be within a certain range, you must first determine whether the clock meets the requirements. It consists of four steps:

1. Calculate the frequency of the master clock first. For the algorithm, see datasheet.

2. Determine whether the frequency meets the requirements through mainclock and preset values (see the input parameters of the function.

3. If required, write the preset value to the PLL control register.

4. The last step is to modify the host clock source as the required PLL. Likewise, it must be divided into two steps.