Clock Skew, clock uncertainly and Period

Pending correction 1.Clock Skewclock Skew = Clock path delay to the destination synchronous element-clock path delay to TE source synch ronous element.

Note that clock skew only mentions path delay, but in practice the phase of the clocks may be different for destination synchronous element and source synchronous element. This shows that the phase of the clock and the clocks skew are two separate concepts. In the preceding offset, the phase behaves as clock arrival time.

is a clock skew example, you can see that the clocks of two triggers are not the same phase, but it is not necessary to calculate clock skew. With the output of DCM as reference, the path delay of the source synchronization element is 0.852+0.860+0.639 = 2.351, the path delay of the destination synchronization element is 0.860 + 0.860 + 0.639 = 2.359. So clock skew = 0.008. The concept of 2.Clock uncertainty clock uncertainty is a good understanding of the clock uncertainty. Clock uncertainties are influenced by several factors, one of which is clock jitter, and the keyword for the clock jitter,period constraint that has an input jitter tells the integrated tool to input the jitter of the clock. Such as

In different cases, the clock uncertainty is calculated differently, such as the DCM clock

Clock uncertainty = [√ (input_jitter2 + system_jitter2) + DCM_DISCRETE_JITTER]/2 + dcm_phase_error

The system jitter defines the jitter of the entire systems and is affected by power supply noise, board level noise, and any external jitter of the system. For clock uncertainty and clock jitter, there seems to be no place to be noticed. 3.Period Analysis

Clock Domains

What is the specific definition of clock domain I am not particularly clear, I think so. For synchronous sequential circuits, there is an unavoidable clock, and the simple thing is that all triggers use a clock. Then you can assume that the entire design path is under the cover of this clock, for example, the path between these two triggers is constrained by the clock period of this clock. This situation is called single clock domain.

But for most designs, this is not the case, for example, DCM can separate clocks from different phases. For example, the clock for the two triggers is not the same at this point, and the data path between the two triggers is connected to the two clocks. What is a clock domain? The field is the area of the clock, which in my opinion is the range of the clock coverage. The path between triggers, one end belonging to Clk20, one end belonging to clk20_90g, spanning two clock domains. Note that these two clocks are generated by a DCM and are clock-dependent, so xst can analyze them. This section does not talk about cross-clock domain issues.

Examples of timing reports

Slack (Setup path): 13.292ns (Requirement-(data path-clock path skew + uncertainty))

Source:intc_2 (FF)

Destination:xorb_2 (FF)

Requirement:15.000ns

Data Path Delay:2.594ns (Levels of Logic = 1)

Clock Path Skew: -0.086ns

Source Clock:clk0 falling at 10.000ns

Destination Clock:clk90 Rising at 25.000ns

Clock Uncertainty:0.200ns

For example, calculate slack. The requirement depends on the relative phase relationship of the two trigger clocks. Notice that the first trigger is sampled on the falling edge, the second trigger is shifted to 90, and the clock period is 20ns. Combined with the relevant concepts mentioned in Setup and offset above. This is very well understood. Unlike the offset constraint, offset is primarily influenced by the relative relationship of external signals, and period is largely dependent on the design. The analysis shows that the limiting factor of the minimum clock cycle is the data path. The data path includes routing delay and logic delay. To understand this, it is helpful to write code later. For example, there cannot be too complicated a logic. (This is because the LUT structure of the FPGA input is limited, take 4 input as an example, logic complex requires LUT cascade, then naturally affect the logical delay)

Clock Skew, clock uncertainly and Period