Configuration space for PCIe devices

There is a lot of information on the configuration space of the PCI device, the following figure is the 64-byte configuration space that the PCI device must support, the range is 0x00-0x3f.

Many PCI devices only support 64 bytes of configuration space. The difference between PCI and PCIe configuration space is as follows.
In addition, the pci/pci-x and PCIe devices also extend the configuration space of 0x40 and 0xFF, which primarily contains capability structures related to the MSI or msi-x interrupt mechanism. All PCIe devices capable of submitting interrupt requests must support the capability structure associated with the MSI or msi-x interrupt mechanism.
PCIe devices also support 0X100-0XFFF this extended configuration space. The extended configuration space for PCIe devices is up to 4KB, and in the extended configuration space of the PCIe bus, some capability structures unique to PCIe are stored, and PCI devices cannot use this space.
In the x86 processor, the Config_address register is used with the Config_data register to access the 0x00-0xff, and eCAM is used to access the 0X000-0XFFF space, while in the PowerPC processor you can use the Cfg_ Data and CFG_ADDR register access to 0X000-0XFFF.
The Pci-x and PCIe bus specifications require their devices to support the capabilities structure. There is a capabilities pointer register in the PCI basic configuration space that holds the head pointer to the capabilities structure list. A PCIe device can contain multiple capability structures, including power management, the structure associated with the PCIe bus, the structure associated with the interrupt request, the PCIE capability structure, and the PCIe extended capability structure