Design of DDR2 interface of Xilinx FPGA spartan3a

1 Introduction

DDR2 (double data rate2) SDRAM is a new generation memory technical standard developed by JEDEC (Joint Committee for electronic equipment engineering). It is the biggest difference from the previous generation of DDR memory technical standards: although the basic method of transmitting data at the same time with the clock rising/falling edge, DDR2 has twice the DDR pre-read capability (that is, 4-bit pre-Access Technology ). In addition, DDR2 also adds the ODT (with built-in core termination resistor) function and built-in appropriate end-to-end resistors to avoid the increase in the cost of making boards due to the large ending Resistors on the chip.

FPGA-based SDRAM Controller, with high reliability, high portability, and easy integration, gradually replaces the previous dedicated controller and becomes a mainstream solution. This paper uses Xilinx Spartan-3A FPGA and Hynix DDR2 SDRAM device hy5ps121621 to design DDR2 controller.

2 FPGA and DDR2 memory Interfaces

Figure 1 shows the interface between DDR2 and FPGA. DDR2 signal lines are divided into clock signal lines CK/ck, data signal line data/dqs/DM, and address signal line address/BA1/ba0; command signal line RAS/CAS/We; control signal line CS/cke/ODT. In addition to connecting all signal lines of DDR2, FPGA also generates External Loop return signal lines (as shown in the dotted line). This signal is output to the input/output module (IOB ), to compensate for iob, device, and trace latency between FPGA and memory.

The differential clock line CK/CK provides a clock for DDR2 data transmission. Data is triggered at both the rising and falling edges of the CK. The bidirectional differential line dqs/dqs is considered as the data synchronization signal, when writing data, it is sent by the Controller. When reading data, DDR2 generates dqs and sends it to the Controller. It is aligned with the read data edge and the write data center. DN shields data that is not stored during burst write transmission. RAS/CAS/we, as the command signal line, sends read, writer, refresh, or pre-charge commands to DDR2; the in-chip termination signal line ODT controls whether DDR2 is required for in-chip termination.

3 DDR2 Controller Design Principle

The FPGA-based DDR2 controller design consists of the Clock generation module, the storage control module, and the read/write data interface module.

The clock of all modules in the Controller comes from the Clock generation module, which is controlled by the digital clock Manager (DCM) and outputs the 90 °, 180 °, and 270 ° clock. This module also contains a delay calibration monitor for calibration of the latency of reading data (DQ) to read data through the pulse (dqs, in this way, the pulse edge can be correctly aligned to the center position of the DQ valid window.

The read/write data interface module is the key to the entire controller design. It is responsible for sending user-written data DQ and DOS to DDR2 according to DDR2 SDRAM timing requirements, DDR2 collects and writes data at every clock edge of dqs. When reading data, DDR2 SDRAM sends dqs and related data to the FPGA that is aligned with the DQ edge. FPGA uses the received dqs signal for delayed calibration as a FIFO write clock for internal storage of read data. FPGA configures a pair of read/write Asynchronous FIFO for each data bit of DDR2, and each data bit is input to the FIFO of the rising and descending edges (ikeo1), as shown in principle 3.

The storage control module is used to generate the address and command signal required by DDR2. DDR2 needs to be initialized before normal read/write operations. Therefore, you need to send the initialization command to DDR2 before sending the read/write command. Read/write access to DDR2 SDRAM is in burst mode. For an emergency write operation, the user needs to provide the write command (user_command), write data (user_input_data), and write address (user_address) signals to DDR2, and send the Emergency Operation completion signal (user_burst_done) at the last write address ), the write operation is terminated when two clock cycles are valid, as shown in burst write sequence 4. The burstable read operation must provide DDR2 with a READ command (User_comm-and) and a read address (User-address), sending an abrupt completion signal (User-burst_done) at the last read address ), the read operation is terminated after two periods of validity, as shown in Figure 5.

4 DDR2 Controller Design and Application

To shorten the development cycle, Xilinx's MIG software tool is used to directly generate DDR2 controller design modules, includingCodeAnd constraints. You can select the template, bus width, and speed level on the MiG GUI, and set key parameters such as CAS latency, burst length, and pin allocation. If the device selected by the designer does not match the template listed in MIG, You can flexibly modify the code after the code is generated to meet the system requirements. Hardware verification is required before the code is added to the project. The test module automatically generated by MIG is used for verification. This module sends a series of write and read commands to the memory, compares the written data with the read-back data, and verifies whether the controller is correct through the comparison signal (led_error. The read data captured by chipscope and the time sequence of related control signals are shown in Figure 6 and Figure 7 respectively. The read/write comparison signal (led_error) Outputs A '0' level when detecting that the read/write data is equal.

After the hardware verification is passed, the Controller code is imported into the system project. The designer only needs to enter the corresponding commands (including read, write, and initialization commands ), the controller module automatically generates command and control signals and sends them to DDR2 according to the DDR2 timing sequence. After the command is sent, a command response signal (user_cmd_ack) is provided to the user ), the designer determines whether the next command can be sent based on this signal. The automatic refresh, activation, and pre-charge commands are automatically executed by the controller without user interference.

5 conclusion

With the help of the MiG tool, 500 Mb/s DDR2 interface data is collected, which occupies 15% iob resources, 17% logic slice resources, and 2 DCM resources respectively. Implement DDR2 controllers in FPGA to save power consumption and space, shorten the system development cycle, and meet the design requirements of most low-cost systems.

 

(Original address: http://www.eefocus.com/article/10-09/2075521283948931.html)