Distributor Interrupt Set/clear-active Registers, Gicd_is/cactivern

The set active register. As the name implies is to put an interrupt to the active state, the clear active register is to clear the active state, here we need to explain some concepts of the interrupt state:

Active state: Assume that the processor is processing the interrupt handler at this time. Then we can say that this interrupt is in active state at this time.

Pending state: Suppose at this time an interrupt has been generated, but the processor has not been processed, then we can say that at this time the interrupt is in the pending state;

Inactive state: If an interrupt is neither an active state nor a pending state, then it is called in inactive state;

Active and pending state: Assume that the processor is running an interrupt handler function. At this point, the interrupt source has an interrupt, so we call this interrupt in the active and pending state;

For set active registers, write 1 is valid, write 0 is invalid, and the read-out value indicates the active state. The assumption is 1, indicating that the interrupt is in the active state at this time. The offset interval for this register relative to Distributor is 0x300-0x37c . The calculation method is:

For interrupt ID m , when DIV and MOD is the integer division and modulo operations:

the corresponding Gicd_isactivern number, N , is given by N = m DIV

The offset of the required Gicd_isactivern is (0x300+ ()
The bit number of the required set-active bit in this register is mMOD.

For the clear active register, write 1 is valid. Write 0 is invalid. The read-out value represents the active state, assuming 1. Indicates that this interrupt is in the active state at this time. The offset interval of this register relative to distributor is0x380-0X3FC, the calculation method is:

For interrupt ID m , when DIV and MOD is the integer division and modulo operations:

the corresponding GICD_ICACTIVERn number, n , is given by n = m div

The offset of the required Gicd_icactivern is (0x380+ ()
The bit number of the required clear-active bit in this register is mMOD.

Distributor Interrupt Set/clear-active Registers, Gicd_is/cactivern