Embedded boot 2: resource-wide and rich Embedded System

The previous article introduced the Starting Process of the resource shortage embedded system, and now introduces the Starting Process of the resource extensiveness embedded system. Generally, memory-wide and rich operating systems are plug-in with SDRAM, And the CPU computing power is relatively strong, such as SoC based on core such as cortex A and MIPS 74k. Is the difference between the two embedded system architectures:

Figure 1 Built-in flash and ram for resource shortage systems. Before power-on, the Code has been written to the built-in flash (nor flas) using a burning tool, and Iram is used for data reading and writing.

Figure 2 shows a resource-wide and rich-type system. Its code is stored in external storage media, such as NAND and SD card, including the Boot Code, OS, root file system, and user data of the boot OS. The running process after power-on is:

1) irom has the first-stage startup code, which is generally called Boot Loader 0 (bl0). It is used to guide the Boot Code in NAND Flash to Iram, the Boot Code in NAND Flash is used to guide the OS code, which is called BL1. When bl0 is powered on, the SDRAM has not been initialized, so it needs to move BL1 to Iram for running. Bl0 has a small amount of code, mainly to solidify the read-driven code of NAND Flash and card, because it must support different startup media.

Due to cost constraints, Iram cannot be very large. The bl0 BL1 migration size is generally fixed and must be smaller than the Iram size. the startup code of the boot OS often exceeds the Iram size, therefore, the boot code of the boot OS is divided into two parts, generally from bl0 to Iram, that is, BL1; the rest is called bl2. Uboot is like this.

2) After bl0 directs BL1 to Iram, the control is handed over to bl1. BL1 initializes the SDRAM and then moves bl2 to the SDRAM.

3) BL1 hand over control to bl2, bl2 then directs the OS, and finally gives control to the OS.

In fact, BL1 will move its BL1 and bl2 together to support different startup modes, such as power-on reset, watchdog interruption, and sleep wake-up. It can be seen that BL1 may run in Iram or in SDRAM. A piece of code has only one link address. How can it run on two different virtual addresses? The answer is that BL1 must be location-independent. The GCC compilation option is-FPIC.

The following blog will analyze the uboot code details in detail-Based on s5pv210.

Embedded boot 2: resource-wide and rich Embedded System