Embedded Boot Two: resource-rich embedded system

This paper introduces the start-up process of resource-scarce embedded system, and introduces the startup process of resource-rich embedded system now.

Memory resource-rich operating system is generally plug SDRAM, and CPU computing power is stronger, such as based on Cortex A, MIPS 74k and other core Soc.

Is the difference between two types of embedded system architectures:

Figure 1, for resource-constrained systems, built-in Flash and RAM.

The code was written to the built-in Flash (nor flas) by the burn-write tool before power-up . The Iram is used for data read and write.

Figure 2 is a resource-rich system. The code is placed on the external storage media, such as NAND. SD cards, including boot code, OS, root file system, and user data for booting the OS.

After power-up the execution process is:

1) Irom has the first stage of the boot code, commonly referred to as boot loader 0 (BL0), The purpose of this is to guide the startup code in NAND Flash into Iram, while the startup code in NAND Flash is to boot the OS code, called BL1.

BL0 power-on execution. The SDRAM has not yet been initialized, so it needs to move BL1 to Iram. BL0 code is relatively small, mainly curing NAND flash and card read driver code. Because it wants to support different boot media.

Because of the cost constraints, Iram can not be very large. That BL0 move BL1 size is usually fixed, must be smaller than the size of Iram. Boot code that boots the OS tends to exceed the iram size. So booting the OS boot code is divided into two parts, the general point is moved from BL0 to Iram, that is, BL1, the rest of the part is called BL2. That's uboot.

2) BL0 Guide BL1 to Iram, give control to BL1. BL1 Initializes a good SDRAM, and then moves BL2 to SDRAM.

3) BL1 gives control to BL2,BL2 then directs the OS, and finally gives control over to the OS.

In fact. In order to support different boot modes. such as power-on reset, watchdog interrupt, sleep wake and so on. In 2), BL1 will move his BL1 and BL2 together to the SDRAM. Visible BL1 may execute in Iram, or it may execute in SDRAM, where a code has only one link address. How is it possible to execute on two different virtual addresses? The answer is that BL1 must be location-independent, and the GCC compilation option is-fpic.

the next blog post will specifically analyze Uboot's code details---based on s5pv210, and welcome attention.

Embedded Boot Two: resource-rich embedded system