External memory interface of the Cyclone II Device

Document directory

• Storage Device
• Interface technical details
• Read operations
• Write operation
• IP address optimized based on the Cyclone II Device

In the new and existing FPGA market, what is Cyclone? The II device extends the role of FPGA in low-cost and large-volume applications. FPGA is now no longer limited to peripheral applications and can execute many key processing tasks in the system. As FPGA is increasingly applied to the data path of the system, FPGA must have interfaces with external memory parts when the system storage requirements exceed the abundant memory resources in the disk.

Based on the successful Cyclone device series, Altera works with industry-leading storage vendors to ensure that users can connect the latest storage devices to the Cyclone ii fpga. The Cyclone II device is designed to be able to use a dedicated interface, and dual data rate (DDR), DDR2, single-speed rate (SDR) SDRAM device, and QDRII) the SRAM device communicates with each other to ensure fast and reliable data transmission. The transmission rate reaches 668 Mbps. Developers can integrate the SDRAM and SRAM devices into their systems within minutes, and run together with the off-the-shelf IP controller cores optimized based on Cyclone II. Table 1 summarizes the support for the Cyclone II External Storage interface.

Table 1: external memory interfaces supported by the Cyclone II Device
Storage Technology	I/O standards	Max bus width	Maximum clock speed	Maximum Data Rate
SDR SDRAM	3.3-V LVTTL	72 bits	167 MHz	167 Mbps
DDR SDRAM	2.5-V SSTL Class I, II	72 bits	167 MHz	334 Mbps
DDR2 SDRAM	1.8-V SSTL Class I, II	72 bits	167 MHz	334 Mbps
QDRII SRAM	1.8-V HSTL Class I, II	36 bits	167 MHz	668 Mbps

Storage Device

Ddr sdram has become popular in recent years, mainly because of its low power consumption, low price, and high bandwidth features. Because data processing occurs along two clock edges, the ddr sdram device is twice the overall effective data bandwidth of the low-speed SDR architecture. The Application of ddr sdram devices is far beyond the personal computer (PC) field. It is now widely used in the fields of networks, communications, set-top boxes, and home entertainment systems. DDR2 memory maintains these features and provides faster clock rate and performance. Industry experts believe that DDR2 will become the dominant DRAM type for many years, because DDR2 has been used as the main memory for PCs.

QDRII (QDRII) SRAM allows system designers to maximize data throughput, mainly in the field of communication applications. The data rate can reach up to 167 MHz. The QDRII architecture features Dual Data ports (input and output). Each clock cycle performs two operations to complete four data commands in each clock cycle. This performance improvement is more significant for applications that are sensitive to bandwidth and latency, such as primary storage used to search tables, linked lists, and controller caches.

For more information about the types of these storage devices, and? It can be obtained from the storage system solution page.

Interface technical details

The Cyclone II device is designed to transmit data input and output at high speed and reliably with external memory devices. The Key Technology of High-Speed interfaces is the use of dedicated I/O features to ensure that all timing requirements are met, and the best performance can be obtained through minimal design consumption.

Each Cyclone II device uses an optimized I/O pin to connect to DDR/DDR2, SDR SDRAM, and QDRII SRAM devices. Each I/O zone has a maximum of two interface signal pins, each containing a single data (DQS) pin and related data (DQ) pin. These pins are designed for high-speed data transmission with external memory devices using SSTL-18 Class I/II, SSTL-2 Class I/II and HSTL Class I/ii I/O standards. Each device can support up to 72 DQ pins with corresponding DQS pins. It supports a dual-sided memory module (DIMM) with 64-bit data and error correction ).

During the read cycle of the dqs circuit, the DQS signal is switched to the optimized clock and data sequence. This circuit does not use the Backtracking delay of the external printed PCB, minimizing the clock skew between the selected DQS and the data DQ signal. This ensures that high-speed DDR memory timing requirements can be reliably met, saving PCB costs. Figure 1 shows the interface between a Typical Cyclone ii fpga and a DDR memory device. Data pins are grouped on the board for cabling. The clock selects the communication number and routes it along with the data group. Each group has one communication number. The IP core of the memory controller of the Cyclone II device generates addresses and control signals and sends them to the on-chip memory. The Cyclone II device also generates a system clock.

Figure 1: Typical Cyclone ii fpga and DDR memory Interfaces

Figure 1 Note:

1. Bidirectional data and selected communication numbers.
2. Select the communication number and connect to the Data Group.
3. The system clock can be generated by PLL.

Read operations

Figure 2 shows the read operation for reading a single data bit from the memory. DQS signals are arranged in the center of the input DQ signal and fed to the global clock network of the device. The DQ signal is sampled by the FPGA register on two sides of the clock, and is synchronized with the system clock through the internal register triggered by the second set of rising edge.

Figure 2: external memory read Operations

Write operation

Figure 3 shows the write operation for writing a single data bit to a storage device. The DQS signal is sent to an external memory device, keeping the difference between the signal and the transmitted data 90 degrees. The output enabling logic is used to meet the time sequence requirements of the front buffer and the back buffer.

The DQ signal is transmitted to the memory device along two edges of the in-phase system clock. A logic register and an output multiplexing are used to switch between data A and data B signals.

Figure 3. external memory write operation

For more information about the external storage interface of Cyclone II, seeCyclone II device ManualInCyclone II device series Data Manual(PDF ).

IP address optimized based on the Cyclone II Device

On the IP macro store page, Altera provides a fully customizable IP macro function controller kernel, which is developed and tested by the Altera and Altera macro function Partner Program (AMPP. Altere also provides users with some storage controller design instances to help them design their own custom storage interfaces. These macro functions allow developers to use Quartus? The intuitive graphical user interface (GUI) in software II allows you to quickly and easily integrate the latest storage Technical Interface in their Cyclone II design. This process automatically configures dedicated external memory features supported by all Cyclone II devices. For apps with demanding time-to-market requirements, the storage controller IP allows developers to focus on product features.