FPGA clock Divider

Http://www.cnblogs.com/fpga/archive/2009/10/24/1589318.html

The duty ratio is 50% divided

Even frequency division is relatively simple

For example, the N-frequency, then count to n/2-1, then the clock flipped, the code is as follows:

1 module even (clk_in,clk_out,rst_n);
2 input clk_in;
3 input rst_n;
4 output clk_out;
5
6 parameter n=6;
7
8 reg [3:0] CNT;
9 Reg Clk_out;
10
Always @ (Posedge clk_in or Negedge rst_n) begin
if (!rst_n) begin
Cnt<=4 ' b0000;
clk_out<=0;
End
+ Else if (cnt==(n/2-1)) begin
clk_out<=~clk_out;
Cnt<=4 ' b0000;
End Else cnt<=cnt+1;
End
Endmodule

The implementation of odd-numbered, respectively, with rising edge count to (N-1)/2-1, then count to N-1, and then with the descending count to (N-1)/2-1, and then count to N-1, to get two waveforms, and then or can code as follows:

1 module Div3 (clk,clk_out,rst_n);
2 input clk,rst_n;
3 output clk_out;
4
5 reg [3:0] cnt_p,cnt_n;
6 Reg Clk_p,clk_n;
7 parameter n=5;
8
9 always @ (Posedge CLK or Negedge rst_n) begin
if (!rst_n)
One by one cnt_p<=4 ' H0;
else if (cnt_p==n-1)
cnt_p<=0;
+ Else cnt_p<=cnt_p+1;
End
16
@ always @ (Negedge CLK or Negedge rst_n) begin
if (!rst_n)
Cnt_n<=4 ' H0;
else if (cnt_n==n-1)
cnt_n<=0;
cnt_n<=cnt_n+1; Else
End
24
@ @ (Posedge clk or Negedge rst_n) begin
if (!rst_n)
clk_p<=1;
-Else if (cnt_p== (N-1)/2-1)
clk_p<=~clk_p;
-Else if (cnt_p== (N-1))
clk_p<=~clk_p;
End
33
@ @ (Negedge CLK or Negedge rst_n) begin
if (!rst_n)
Approx. clk_n<=1;
PNS Else if (cnt_n== (N-1)/2-1)
clk_n<=~clk_n;
if (cnt_n== (N-1))
clk_n<=~clk_n;
The end
Assign clk_out=clk_n|clk_p;
Endmodule

FPGA clock Divider (RPM)