FPGA comprehensive Encoding

1 Decision Tree

The IF else statement and case are used in FPGA.

A) if else is privileged, similar to priority encoding (when the two conditions are both true, only the first condition is true). Therefore, the IF else structure should be used when there are privileged conditions, the privileged order of parallel if condition statements is exactly the same as that of if else.

B) case statements are often (not always) used in conditions where all conditions are incompatible. However, by default, case is still privileged, and the compiler selects additional logic to generate the privileged logic. If we determine that the condition is mutually exclusive, we can use the pseudo command 'parallel _ case' to implement a fully parallel structure.

C) if case is the default condition, the current value is maintained when all conditions are not met. We can also use the pseudo command full_case to cancel the default condition.

2. blocking assignment can simulate the combination logic, while non-blocking assignment can simulate the time series logic. However, blocking and non-blocking cannot be mixed into an always module.

3. For loop can be used to compress statements with the same functions.

4. IDEF should define global exploitation.

5. The parameters should be partially exploited and converted from modules to modules.

6. The passing of naming parameters is superior to passing of location parameters or deparameter.