FPGA computer (reconfigurable computing)

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What Should FPGA Computers look like?

As one of the typical non-Feng nuoman computing architectures, FPGA-based computing systems are undoubtedly very attractive. The existing solutions have not actually left the framework of the Von noriman machine. For example, FPGA is used as the reconfigurable coprocessor of the traditional CPU, or the soft-core CPU (von noriman Virtual Machine) is made in FPGA ).It is worth looking forward to when the FPGA computing platform can get rid of such limitations and truly use its own characteristics to form an advanced computing platform in the future..

FPGA-based computing platforms should have the following features:

1. Dynamic Local reconfiguration.This part can be part of the logic in an FPGA chip or a part of the FPGA chip array. The system allocates new logical resources as needed to form new logical components to complete new computing tasks and release the logical resources occupied by completed tasks. The optimal time granularity for such switching remains to be determined, which is different from that for traditional CPU multi-task switching. In the future, we will use new/Delete to allocate the entire logical circuit. The new process is (CodeSegment ?) Load the configuration data to the specified address of the FPGA Configuration memory and mark the block configuration memory as used. Delete deletes the configuration data. With the increase of abstraction, introducing garbage collection may become inevitable.

2. Primary and secondary storage of the new structure.As always, the primary storage is played by a large number of DRAM resources, but its structural details and usage will change from traditional storage to traditional storage. One of the typical features is the width of the data port. Because FPGA does not have the sequential read/write feature of traditional CPUs, it mainly reads and writes configuration data in large blocks, with a granularity of KB ~ MB level, while small-scale and frequently-used data storage tasks in the computing process are largely undertaken by the internal SRAM units of FPGA. In this way, DRAM tends to have a wider data port and a more coarse-grained addressing method. For example, the primary storage may be edited by PAGE (4 kb). After the page number is given, the whole page data can be read and written in a highly optimized DMA mode. The high-speed cache of the primary storage will also make similar changes. Like traditional systems, the system focuses on hard disks and flash memory, but the executable files are not stored as command sequences, but as a collection of configuration data. When you double-click the executable file icon, the system loads the code segment and data segment to the primary storage, and loads the process image to the FPGA at the appropriate time according to the process scheduling. After the time slice arrives, the image will be written back to the primary storage, waiting for the next scheduling. Since process scheduling involves much greater data transmission than traditional systems, an effective new process switching mechanism will be introduced.

3. The minimum number of peripheral I/O devices.The number of various I/O controllers will be greatly reduced,Because everything can be made in FPGA.And far higher flexibility. The only reason for the need for peripheral circuits isAnalog Signal. Various digital signal interfaces can be directly connected to the fpga I/O pins through level conversion, and even the anti-jitter processing of the keyboard does not require a dedicated chip. The logic that FPGA directly connects to these pins is called a hardware driver, and the configuration data is the driver software. Common application writers do not need to be interested in Interface Details, but only need to interact with these driver software.

4. A complete and hierarchical software system with new structures.APIS composed of logical signals form standard documents. application software writers can directly call these APIs in a simple way without considering low-level information such as hardware timing.ProgramThe dominant idea of design can be a state machine or a higher level of abstraction. High concurrency is a constant topic, and the traditional sequential execution programming model will become a highly abstract, or "sequence-oriented programming (SOP )". The above are the results of current thinking, and the compatibility with traditional systems is not considered for the moment. Hope to discuss with you and get to know each other.