FPGA face questions and answers

Han Wang written test
　　
Here are some basic digital circuit knowledge questions, please answer them briefly.
　　
A) What is setup and holdup time.

1 Settling time refers to the time at which the signal arrives at the trigger input before the clock-sensitive edge reaches the trigger, and only the hold-time signal is satisfied to be saved to the trigger correctly.

2 hold time refers to the time at which the data needs to be stabilized after the clock edge arrives, which is another indicator that the data can be saved to the trigger.

b) What are the phenomena of competition and risk-taking? How to judge. How to eliminate.

1 competition refers to the logic circuit due to inconsistent delay time in the circuit resulting in inconsistent signal arrival time is called competition.

2 The glitch generated by the competition in logic circuits is called adventure.

3 Direct observation of the existence of mutual exclusion in the logic circuit, through the Carnot graph to see if there is an edge-relative situation.

4 can increase the complementary product term, add filter capacitance at the output, and adopt the sequential logic;

c) Draw a logic circuit that achieves twice times the frequency of the D trigger.

The D-Trigger's Q-side is connected to the D-end, and the clock is connected to the D-trigger.

D) What is "line and" logic, and what specific requirements are there for hardware features to implement it?

A: line and logic refers to the function that the two lines can be directly connected to. In the hardware need OC door, if not using OC door will cause the gate circuit tube electric flow through large and burned logic gate.

e) What is synchronous logic and asynchronous logic.

A: The synchronization logic refers to the entire logic circuit is operating under the same clock, only when the clock is valid, the change in logic will be effective, other changes in time will not cause the logic of the other device changes.

Asynchronous logic means that there may be multiple clock signals in the logic circuit, or there is no clock signal, and a logic change in the circuit may cause the whole circuit logic to change.

f) Please draw a microcomputer interface circuit, a typical input device and microcomputer interface schematic diagram (data interface, control interface, storage/buffer).

For:... g) You know those common logic levels. Can the TTL and COMs levels be directly interconnected?
Ttl,lvttl,cmos,lvcmos, no, TTL can not drive Cmos,cmos can drive TTL;
2, programmable logic devices in modern electronic design is becoming more and more important, please ask:

A) What are the programmable logic devices that you know about?

PLA,CPLD,FPGA; b) Try vhdl or Verilog, able describe 8-bit D trigger logic.

Module D8 (

Input CLK,

input [7:0] din,

Output [7:0] Q,QF;

);

REG[7:0] Q;

Always @ (Posedge CLK)

Q=qin;

Assign qf=~ (q);

Endmodule 3,
Imagine that you are designing an electronic circuit solution. Please describe the entire process of designing (including schematics and PCB diagrams) with EDA software (e.g. Protel) to debug the prototype. In each link should pay attention to what problems.
Whether the conductor width in the PCB can support the current requirements, whether there is a short circuit or a circuit breaker ...
　　
3. The setup,hold time of the Reg is given, and the delay range of the intermediate combinational logic is obtained. Setup/hold
Time
Is the time required between the test chip and the input signal and the clock signal. The settling time refers to the time when the clock signal of the trigger rises along the arrival of the data before the date is stable. The input signal should advance the clock rising edge (as the rising Edge is valid) T time to reach the chip, this T is the settling time-setup
Time. If setup time is not met, the data cannot be hit by this clock, only the data can be hit by the next rising edge of the clock.
Hold time refers to the time when the data is stable when the trigger's clock signal rises along the arrival. When hold time is not enough, the data cannot be driven into the trigger.