FPGA Development--commissioning

Original link:

FPGA Development 13: FPGA Practical Development Skills (12)

FPGA Development 13: FPGA Practical Development Skills (12)

5.6 Commissioning experience in large scale design

In large-scale design debugging should be in accordance with the design concept in reverse order, from the bottom test, mainly rely on the Chipscope Pro tool. The following is mainly about the use of Chipscope Pro, FPGA Editor components.

5.6.1 Chipscope Pro Component Application Example

In the Turing Software Design tool, ISE integrates all of Xilinx's tools and programs. Chipscope Pro is no exception, as a class of source files in Ise, and the status of HDL source files, IP Core, and embedded systems is equivalent. This section implements a counter module on the Xilinx spartan3e-d board, based on the module detailing how to create a new Chipscope application in Ise and detailed operations for observing and analyzing data.

Example 5.6.1: Implement a 8-bit counter in ISE and analyze its logical output with Chipscope.

(1) Create a new user project, add the MYCOUNTER.V source file, and its contents are listed as follows:
Module MyCounter (CLK, Reset, dout);
Input CLK;
Input reset;
Output [7:0] dout;
reg [7:0] dout;
Always @ (Posedge CLK) begin
if (reset = = 0)
Dout <= 0;
Else
Dout <= dout + 1;
End
Endmodule

Then, according to the circuit connection, add the corresponding pin constraints.

(2) Comprehensive project, then in the ISE Project Management area, right-click, select the "Add New Source" command, in the popup dialog box select "Chipscope Definition and Connection File" type, and in the "File Name" field to enter Chipscope is shown in design name mychipscope,5-41.

Figure 5-41 Adding the Chipscope design

Figure 5-42 Test Module selection Interface

Click on the "Next" button to enter the analysis file selection interface, where all the HDL design, schematic design is listed (including the top level module and all the underlying modules) for the user to select, with a mouse click can be selected, this example select Mycounter,5-42. Click "Next" button to enter the summary page, click "Finish" button to complete the Add.

(3) Double-click the Sub-module MYCHIPSCOPE.CDC under MYCOUNTER.V of the project area to automatically open Chipscope Pro Core insterser software, add trigger unit and trigger bit width. Where the trigger type is selected as basic, the bit width is 8 bits, and the sampling depth is set to 4096, as shown in steps 5-43 through Figure 5-46.

Figure 5-43 Debug Engineering Configuration Interface

Figure 5-44 icon Core Configuration Interface

Figure 5-45 Trigger Signal Configuration Interface

Figure 5-46 Acquisition Depth Configuration interface

(4) Click "Next" to enter the Web table connection Display page, 5-47 shown. Where the user-defined trigger and clock signal lines are not connected, the words "UNIT", "Clockport" and "Triggerports" in the figure are displayed in red, and when the connection is completed correctly, it becomes black.

Figure 5-47 Web table connection prompt interface

Click the "Modify Connection" button in Figure 5-47, enter the connection page, the clock and data connection 5-48, figure 5-49 shows. It is important to note that the Chipscope Pro can only analyze the internal signal of the FPGA design and therefore cannot directly connect the input signal to the grid, so the input signal network table is all in gray display. If the input signal is to be sampled, it can be realized by connecting its input buffer signal, the clock signal chooses the corresponding BUFGP, the common signal chooses the corresponding ibuf. As shown in 5-48, when the sampling clock is selected, CLK_BUFGP is selected.

Figure 5-48 Clock Grid connection interface

Figure 5-49 triggering the grid table connection interface

After the connection is complete, click "OK" button to return to the connection display interface, find all the prompt characters "UNIT", "Clockport" and "triggerports" No red, then click "Return Project Navigator", Exit Chipscope, Return to the ISE. Otherwise you need to click "Modify Connection" button again to reconnect.

(5) Add UCF files to the project to constrain the clock and data pin position. To simplify, you can add only the pin constraints for both the CLK and reset control signals, with the following contents:

NET "CLK" LOC = "C9" | Iostandard = LVCMOS33;
# Define Clock period for the oscillator (40%/60% duty-cycle)
NET "CLK" PERIOD = 20.0ns high 40%;
NET "reset" LOC = "H13" | Iostandard = LVTTL | PULLDOWN;

(6) In the ISE Process Control area, double-click "Implement Design" and "Generate programming file" to complete the implementation and generate the programmable files, and the various cores inserted by the designer will also be included in the bit file. Once the configuration file is generated, double-click the Analyze Design Using chipscope icon shown in Figure 5-50 to automatically open the Chipscope Pro Analyzer software.

Figure 5-50 Chipscope Pro Analyzer Start action

(7) on the Chipscope Analyzer user interface, click on the toolbar labeled "" to initialize the boundary scan chain. When the scan is complete, click the dev:0 My Device0 (xc3s500e) →configure command under the Device menu to select the. bit file to configure the FPGA.
(8) After the chip configuration is complete, select the "File" menu "Import" command, you can pop up the CDC file loading page, select the appropriate CDC file, will be all the "dataport" name modified to the integrated network name.
(9) Combining CNT bus signal. You can press and hold the "Ctrl" key, select multiple bus signals, right-click, select the "Add to Bus" command to combine them into the corresponding bus signal, 5-51.

Figure 5-51 Adding a bus operation

(10) Do not set trigger conditions to collect data. Click on the "" icon in the toolbar to start collecting data. As shown in the overall result 5-52, click the button on the toolbar to enlarge the signal, as shown in the local result 5-53. It can be seen from the analysis results that this design successfully completed the function of 8-bit counter in FPGA.

Figure 5-52 Analyzer analysis results as a whole

Figure 5-53 Analyzer Analysis Results Local

(11) Set trigger conditions to collect data. The value column of the "M0:trigger Port0" row in the match area of the "Trigger Setup" column enters the trigger condition "0000_0000", as shown in 5-54.

Figure 5-54 Trigger Condition setting interface

Click on the "" icon in the toolbar to start collecting data, you can see that the first number of results is 0, 5-55 is shown. Of course
Users can set more complex trigger conditions as needed.

Figure 5-55 Trigger Condition setting interface

(12) Using bus plot function to draw output signal waveform. Double-clicking the "bus Plot" command in the project area and selecting "Dout" in the "bus Selection" area of the pop-up window will display the collected data graphically, as shown in 5-56. Since this design is a 8-bit plus 1 counter, the waveform is a sawtooth wave with a amplitude of 0 to 255.

Figure 5-56 8 The waveform of the counter

FPGA Development--commissioning