FPGA implementation of trapezoid forming algorithm

Cont. ~ ~ ~ trapezoid forming algorithm, on the stick is the principle of simulation and software implementation, this paste is a hardware implementation.

Break down the system functions into 4 sub-modules:

H (z) =h1 (z) *h2 (z) *h3 (z) *h4 (z)

In the formula:

H1 (z) = (1-qz-1)/(1-Z-1);

H2 (z) =1-z-k;

H3 (z) =1-z-1;

H4 (z) = (1/ta) * (z-1)/(1-Z-1)

There is a sequential problem with the cascade of 4 sub-modules, to avoid the overflow of subsystems with peak gain or to enlarge the quantization noise. So put the H1 on the first level; H4 is the integral unit, in order to avoid overflow, put it at the last level; H2, H3 are placed in the middle, because their structure is the same, so the position can be interchangeable.

Structure design of H1 sub-module

The structure design is to describe the linear constant coefficient equation by using the interconnection structure of the arithmetic modules such as adder, multiplier and delay unit, the system resources which are consumed by different structure design and the performance are very big difference. The structure design of the H1 sub-module can be realized by IIR filter.

Structural design of H2 andH3 sub-modules

The structure design of the H2 and H3 sub-modules is shown in the diagram .

Structure design of H4 sub-module

The structure of the H4 sub-module is shown in the design diagram .

Algorithm FPGA implementation:

The system RTL module diagram is as follows:

The filter is observed using the Quartus II signal TAP II (embedded Logic Analyzer). Signal TAP II input/output signal as shown. The output of the Signal Tap II shows that the trapezoidal forming filter can stably convert the input exponential signal into a trapezoidal pulse signal. The digital signal processing of the FPGA needs to quantify the parameters, where the numerical value of E-nts/tao is difficult to quantify accurately, and studies have shown that the quantization accuracy of this numerical value directly affects the accuracy of trapezoid forming, and my simulation also validates this conclusion (the flat top of the trapezoid will produce distortion). Comparing the results of time series simulation with MATLAB simulation results, the output accuracy of the trapezoidal forming filter with FPGA design is quite satisfactory.

Program:

I'll put it up tomorrow. Definitely post!!!

FPGA implementation of trapezoid forming algorithm