FPGA Reset Circuit Design

The reset circuit is very important to both FPGA and ASIC, because a poor reset circuit may lead to non-repeated faults.

1. Problems Caused by full Asynchronous Reset

Full Asynchronous Reset is asynchronous when it is established and released, which may bring the system into quasi-steady state.

2. Full synchronization Reset

3 asynchronous establishment and synchronous release of the circuit will provide more reliable reset than the fully synchronous or asynchronous circuit.

The Code is as follows:

Module reset (

Input CLK, rst_n,

Output Reg asy_rst

);

Reg R1;

Always @ (posedge CLK or negedge rst_n)

If (! Rst_n) begin

R1 <= 0;

Asy_rst <= 0;

End

Else begin

R1 <= 1;

Asy_rst <= R1;

End

Endmodule

4. Different types of Reset should be implemented in multiple always. For example, the reset of the descent edge and the reset of the rising edge should be separated, or bilateral reset or level reset are possible.

5 The risk of internal logical circuits may also lead to system reset.

6. Separate reset synchronizers should be used for different clock domains.