I2C and SPI Bus compare __ Hardware

The last 2 weeks have been debugging IIC and SPI bus equipment, here record 2 kinds of bus, in case of forgetting.

One IIC Bus

The abbreviation of I2c--inter-ic serial Bus is the serial transmission bus between chips introduced by Philips company. It implements duplex synchronous data transfer with 1 serial data cables (SDA) and 1 serial clock lines (SCL). The utility model has the advantages of less interface line, simpler control mode, smaller device encapsulation form and higher communication rate. In the master-slave communication, multiple I2C bus devices can be connected to the I2C bus at the same time to identify the communication object by address.

The protocol of the IIC interface includes the device address information, which can connect multiple devices from the same bus, and exchange data and commands by answering. But the transmission rate is limited, the standard mode can reach 100Kbps, fast mode can reach 400Kbps (our development Board is generally in 130Kbps), high-speed mode to achieve 4Mbps, can not achieve full duplex, not suitable for transmission of a lot of data.

IIC Bus is a real multi-host bus, the bus on a number of host initialization transmission, can be transmitted through detection and arbitration to prevent data damage.

Down to learn more about IIC Bus timing:

1.1 Bus Data availability

The IIC bus is simplex, so the data at the same time has only one flow, so the sampling valid clock is also single and is the high level sampling data at the SCL clock.

IIC Bus SDA data at the SCL clock low level can be changed, but in the clock high power must be stable at ordinary times, so that the master and slave devices according to the clock sampling data, the following figure:

1.2 Bus idle condition IIC Bus devices all release the bus (issue the transmission stop), the IIC bus according to the pull resistor into a high level, SDA SCL are high level.

1.3 Bus data transfer start and end conditions

IIC bus SCL high power peacetime SDA appear from high to low jump, flag on the bus on the starting condition of data transmission

IIC bus SCL high power peacetime SDA appear from low to high jump, flag on the bus to the end of data transmission conditions

1.4 Bus data transmission order and ACK response

IIC bus on the data transmission room MSB before, LSB in the rear, from the oscilloscope, read from left to right in turn

The IIC bus transmits the data not to accept the limit, but each send to the SDA must be 8 bits, and the host sent 8-bit after the release of the bus, from the machine received data must be pulled low SDA a clock, response ACK indicates the success of the data received, we if the oscilloscope saw the waveform is each time 9-bit data, 8bit+1bit Ack. As follows:

When a byte of data is received from the machine, if some time is required, the SCL is lowered, the transmission enters the waiting state, the process completes, the SCL is released, and the transmission continues, as follows:

1.5 bus Read and write timing

The transmission of the data after the starting condition sends a 7-bit address from the machine, followed by the data direction (R/W), 0-indicating that the data is sent (write), and 1-represents the receiving data (read). Data transfers are typically terminated by a stop bit (P) generated by the host. However, if the host still wants to communicate on the bus, it can produce a duplicate start condition (Sr) and address another from the machine, rather than first generating a stop condition. In this transmission, there may be a combination of different read/write formats.

IIC Bus main equipment read and write from the device, generally with the device from the register, this can be read from the device's datasheet to obtain. The bus write sequence is as follows:

Master Start + master Addr|w + slave ack + master Reg|w + slave ack + master data + slave ack + master restart. Master Data + slave Nack + master stop

Bus reading sequence is as follows:

Master Start + master Addr|w + slave ack + master Reg|w + slave ack + Master restart + master Addr|r + slave ack + slave D ATA + Master Nack + master Stop

The difference between the bus reading sequence and writing is that it requires 2 transmission to complete a read, the first to write register address to the device, is actually written from the device control registers or command registers, from the device within the address to be addressed to the Register to operate.

I read our BIOS and the kernel found that 2 in the bus read the timing of the implementation is not the same, in the first register address write, a hair is restart, a hair is stop, and then start reading data, oscilloscope catch waveform found that read data are correct, This shows that all 2 of these timing are correct.

The IIC bus's reading and writing time is fixed, the equipment communication strictly follows the protocol, so the writing of the IIC bus device driver is relatively simple.

The main applications of IIC bus equipment are touchscreen RTC external extension IO, etc.

Two SPI bus

Spi--serial peripheral Interface, serial peripherals interface, Motorola introduced a synchronous serial communication mode, is a three-wire Stang, because of its strong hardware function, SPI-related software is quite simple, Gives the CPU more time to handle other transactions.
SPI usually has a sck clock, STB slice selection, data signal three signals. I2C usually have SDA data and an SCL clock of two signals.

SPI bus really achieve full duplex data transmission, SPI has 3 lines and 4 lines two, 4 lines, is more than a line called SDC, to tell from the device is now transmitting data or instructions. This interface is faster and can transmit more contiguous data. To connect multiple devices, the SPI needs to equip each device with a single slice of the signal. If you want to achieve full-duplex, you need to add a single data line (Mosi MISO).

This means that the SPI bus is selected from the device by slice selection.

The SPI bus speed is faster than IIC, our development board can reach 30MHZ fastest.

SPI Bus Features:

1. master-from Mode (Master-slave) control mode
SPI provides that communication between two SPI devices must be controlled by the primary device (master) for the secondary device (Slave). A master device can control multiple Slave devices by providing Clock and slice selection (Slave Select) for Slave devices, and the SPI protocol also stipulates that Slave of Clock equipment is provided by Master equipment through SCK pins Slave equipment, Slave device itself can not produce or control Clock, no Clock Slave equipment does not work properly.

2. Use synchronous mode (synchronous) to transmit data
The Master device generates the corresponding clock pulse (Clock Pulse) based on the data to be exchanged, the clock pulse consists of a clock signal (Clock Signal), and the clock signal is controlled by the clock polarity (CPOL) and the clock phase (CPHA) to control when data is passed between two SPI devices Exchange and when the data received to sample, to ensure that the data between the two devices is synchronous transmission.

3. Data interchange (exchanges)
The data transfer between SPI devices is also referred to as transmitter, because the SPI protocol provides that a SPI device cannot only act as a "sender" or "receiver" (Receiver) in the data communication process. That is, Full-duplex, in which the SPI device sends and receives a bit sized data for each Clock cycle, which is equivalent to a bit sized data being exchanged.
A Slave device must be able to be accessed by a master device before it can receive a control signal from master. Therefore, the Master device must first select the Slave device through the Ss/cs pin and select the Slave device that you want to access.
In the process of data transfer, each received data must be sampled before the next data transfer. If the previously received data is not read, then the data that has been received may be discarded, causing the SPI physical module to eventually fail. As a result, the data in the SPI device is typically read in the program after the SPI is transmitted, even though the data (Dummy) is useless in our program.

The specific SPI working principle can see another article in the blog

SPI and IIC are 2 different communication protocols and are now widely used in communication between ICS. And a lot of SCM has been the whole and SPI and IIC excuses. But like 51 this does not support SPI and IIC SCM, can also use the analog clock to work the SPI and IIC communication.

Here is a summary of the similarities and differences between the 2 bus:

1 IIC bus is not Full-duplex, 2-line SCL SDA. SPI bus to achieve full duplex, 4-wire sck CS Mosi MISO

The 2 IIC bus is a multihomed bus that is locked from the device via the address information on the SDA. The SPI bus has only one main device, the main device is selected by the CS slice to determine the device

3 IIC Bus transmission speed in 100kbps-4mbps. SPI bus transmission speed faster, can reach more than 30MHZ.

4 IIC Bus idle state SDA SCL are high level. SPI bus idle state Mosi miso is also sck is a Cpol decision.

5 IIC Bus SCL high power peacetime SDA descent along the sign transmission begins, rising along the sign transmission end. SPI bus CS Pull low flag transmission start, CS pull high flag transmission end

The 6 IIC bus is an SCL high level sample. The SPI bus, which is full duplex, is sampled along the Cpha, depending on the decision. Generally the master device is sck to the rising along the sending, the descent along the collection

7 IIC Bus and SPI bus data transmission are MSB in front, LSB in the rear (serial port is LSB in front)

8 IIC Bus and SPI bus clocks are generated by the main device and only emit a clock when data is transmitted

9 IIC Bus Read and write timing is more fixed and unified, the device driver is easy to write. SPI bus different from the device reading and writing time difference is relatively large, it must be based on the specific equipment datasheet to achieve reading and writing, relatively complex.

from: http://blog.csdn.net/skyflying2012/article/details/8237881