I2C bus protocol details

I2C bus Definition The I2C (Inter-Integrated Circuit) bus is a two-line serial bus developed by Philips to connect the microcontroller and its peripheral devices. The I2C bus was created in 1980s and was initially Audio and video devices Development is now mainly used in server management, including communication of the status of a single component. For example, the administrator can query each component to manage system configurations or master the functional status of the component, such as power supply and system fan. Multiple parameters such as memory, hard disk, network, and system temperature can be monitored at any time, which increases system security and facilitates management. I2C bus features The main advantage of I2C bus is its simplicity and effectiveness. Because the interface is directly on the component, the space occupied by the I2C bus is very small, which reduces the space of the circuit board and the number of chip pins, and reduces the interconnection cost. The length of the bus can be up to 25 feet And supports up to 40 components at a transmission rate of 10 Kbps. Another advantage of the I2C bus is that it Multi-controller supported (Multimastering), in which any device that can send and receive can become the master bus. A master can control signal transmission and clock frequency. Of course, there can only be one master at any time point. How I2C bus works Bus composition and signal type
The I2C bus is a serial bus consisting of the SDA data line and the clock SCL, which can send and receive data. Two-way transmission is performed between the CPU and the Controlled IC, and between the IC and IC. The maximum transmission rate is 100 kbps. Various controlled Circuits are connected in parallel on this bus, but just like telephones, only dialing their respective numbers can work. Therefore, each circuit and module has a unique address, in the process of information transmission, each module circuit connected to the I2C bus is both the master controller (or controller) and the transmitter (or receiver), depending on the functions it wants to accomplish. The control signals sent by the CPU are divided into address codes.
The address code is used for site selection, that is, the circuit to be controlled is connected to determine the type of control. The control variable determines the type (such as contrast and brightness) of the adjustment and the amount to be adjusted. In this way, each control circuit
Although they are mounted on the same bus, they are independent from each other and are irrelevant to each other. The I2C bus has three types of signals during data transmission: start signal, end signal, and response signal. Start signal: In high-power mode, SDA switches from high to low and starts to transmit data. End signal: In high-power mode, SDA changes from low-level to high-level and ends data transmission. Response signal: After receiving 8-bit data, the IC that receives the data sends a specific low-level pulse to the IC that sends the data, indicating that the data has been received.
Data. After the CPU sends a signal to the controlled unit, it waits for the controlled unit to send a response signal. After the CPU receives the response signal, it determines whether to continue to transmit the signal based on the actual situation. If no response is received
Signal, which is determined to be a fault in a controlled unit. Among these signals, the start signal is required. Either the end signal or the response signal can be used. At present, many semiconductor integrated circuits have integrated I2C interfaces. Single-Chip Microcomputer with I2C interfaces include: cygnal's c8051f0xx series, philipsp87lpc7xx series, and microchip's pic16c6xx series. Many peripheral devices, such as memory and monitoring chips, also provide I2C interfaces.
A bus is a two-way two-wire bus used for the connection between IC Devices. It can be mounted with multiple devices and connected through two wires, occupying a very small space, the length of the bus can be up to 25 feet, and the maximum transmission rate of 10 Kbps can support four components. Its other advantage is that multi-controller, as long as the devices that can receive and send can become the master controller, of course, multiple masters cannot at the same time
Work. The I2C bus has two signal lines, one of which is SDA (data line) and the other is SCL (clock line ). Clock signals are generated by the master device at any time. I2C bus operation
I2C procedures use Master/Slave bidirectional communication. When a device sends data to the bus, it is defined as a sender, and the device receives data as a receiver. Both the master device and slave device can work in the receiving and sending status.
The bus must be controlled by the main device (usually a microcontroller). The main device generates a serial clock (SCL) to control the transmission direction of the bus and generates Start and Stop conditions. The data status on the SDA online can be changed only during the period when the SCL is low. During the period when the SCL is high, the SDA status change is used to indicate the start and stop conditions.
Control byte
After the start condition, it must be the control byte of the device, where The four-digit high is the device type identifier (different chip types have different definitions, and the eeprom should generally be 1010) Then, the three digits are selected as slices, and the last digit is the read/write bit. When the value is 1, the read operation is performed, and when the value is 0, the write operation is performed.
Write operation
Write operations are divided Byte writing and page writing The two operations vary depending on the size of each loaded byte of the chip.
Read operations
There are three basic read operations: Current address read, random read, and sequential read . Figure 4 shows the sequence of sequential reads. It should be noted that the 9th clock cycles of the last read operation are not "irrelevant ". To end the read operation, the host must issue a stop condition between 9th cycles or maintain SDA as high within 9th clock cycles, and then issue a stop condition. I2C bus application At present, many semiconductor integrated circuits have integrated I2C interfaces. Single-Chip Microcomputer with I2C interface: cygnal
C8051f0xx series, Samsung's s3c24xx series, philipsp87lpc7xx series, and microchip's pic16c6xx series. Many peripherals
Devices such as memory and monitoring chips also provide I2C interfaces. I2C device/I2C Device 1. Storage Class: At24cxx series EEPROM of ATMEL ;
2. I2C bus 8-bit parallel I/O port expansion chip pcf8574/jlc1562;
3. I2C interface real-time clock chip ds1307/pcf8563/sd2000d/m41t80/me901/isl1208 /;
4. I2C Data Acquisition ADC chip mcp3221 (12 bitadc)/ads1100 (16 bitadc)/ads1112 (16 bitadc)/max1238 (12 bitadc)/max1239 (12 bitadc );
5. I2C interface digital-to-analog conversion DAC chip dac5574 (8 bitdac)/dac6573 (10 bitdac)/dac8571 (16 bitdac )/;
6. I2C interface temperature sensor tmp101/tmp275/ds1621/max6625 Dedicated USB to I2C chip: usb2i2c Usb2i2c is an interface chip for converting USB Bus to I2C bus I2C/IIC/Twi/SMBus, the USB 2i2c chip can be used to conveniently communicate between the USB bus of the PC and the I2C interface of the lower computer (IIC or Twi Bus: SCL line and SDA line.
The PC end of the USB 2i2c chip provides easy-to-use usbiox. dll dynamic library calling, which can be conveniently called by the development tools of the upper computer, such as VB, Vc, Delphi, LabVIEW, and BCB. Related Routines can be found on the usbio website.
Features:
● Full-speed USB device interface, compatible with USB V2.0.
● The peripheral components are simple. Only one 12 m crystal and two capacitors are needed.
● Low cost: the connection between the upper computer and the lower computer can be directly achieved through the I2C bus, without the need for auxiliary MCU.
● The host computer software can flexibly implement various operations of I2C/IIC/Twi bus protocols.
● As the I2C bus host/Master host.
● The I2C interface provides the SCL and SDA signal lines, and supports four different clock transmission speeds: 100 kHz/400 kHz/750 kHz.
● Small SSOP-20 encapsulation.