I2C bus signal timing Summary

I2C bus signal timing Summary

Idle bus status
The SDA and SCL signal lines of the I2C bus are in the idle state at the same time.At this time, the output-level FET of each device is in the cutoff state, that is, the bus is released.By the two signal lines of the respective pull-up resistance to raise the level.

 

Start Signal
The SDA level of the data line is lowered (that is, the negative hop) during the high-level period of the clock line SCL, which is defined as the start signal of the I2C bus, it marks the beginning of a data transfer. The start signal is a time series signal of Level Jump, rather than a level signal. The start signal is automatically set up by the master controller. The I2C bus must be idle before the signal is established.
Restart Signal
After a data communication (send or receive) is completed during the master control bus, if you want to continue to use the bus for another Data Communication (send or receive) without releasing the bus, it is necessary to re-start the SR signal timing. The restart signal Sr is the end of the previous data transmission and the start of the next data transmission. The advantage of the restart signal is that the master controller does not need to release the bus between the two communications, so that the control of the bus is not lost, that is, other master device nodes are not allowed to seize the bus.

 

Restart Signal
After a data communication (send or receive) is completed during the master control bus, if you want to continue to use the bus for another Data Communication (send or receive) without releasing the bus, it is necessary to re-start the SR signal timing. The restart signal Sr is the end of the previous data transmission and the start of the next data transmission. The advantage of the restart signal is that the master controller does not need to release the bus between the two communications, so that the control of the bus is not lost, that is, other master device nodes are not allowed to seize the bus.

 

Stop Signal
During the High-level period of the clock line SCL, the SDA of the data line is released, so that the SDA returns a high-level (positive jump), known as the I2C bus stop signal, marking the termination of a data transmission. The stop signal is also a time series of Level Jump, rather than a level signal. The stop signal is also established by the master controller. After the signal is established, the I2C bus returns idle status.

It is not specified in the Data Validity that SDA can only change at the low level of the SCL. Why is the difference between star and stop? First, star and stop are not data, so they do not comply with the rules in Data Validity. Other data is observed, while Star and stop "do not comply" lead to easier identification of star and stop. This is more advantageous than non-compliance.

The Start and Stop conditions are generally generated by the host. The bus is considered busy after the start condition. after a certain period of time, the bus is considered idle again.

If a duplicate start (SR) condition is generated without a stop condition, the bus will remain busy. In this case, the start condition (s) and the repeat start condition (SR) are functionally the same.
If the devices connected to the bus combine the necessary interface hardware, it is easy to use them to detect the start and stop conditions. However, a microcontroller without such an interface needs to sample the SDA line at least twice in each clock cycle to determine whether a level switch has occurred.

 
Data bit Transfer
Each bit of data transmitted on the I2C bus has a corresponding clock pulse (or synchronous control), that is, with the combination of the SCL serial clock, each bit of data is serialized on SDA. During data transmission, the SDA level must be stable during the high-level period of the SCL. The low level is DATA 0, and the high level is data 1. The SDA level change status is allowed only when the SCL is low. The level of logical 0 is low, while the level of logical 1 depends on the positive Supply Voltage VDD of the device itself (when using an independent power supply ). Data bit transmission is triggered by edge.

 

 

Response Signal
All data on the I2C bus is transmitted in 8 bytes. Each byte sent by the transmitter releases the data line during the time pulse 9, and the receiver returns a response signal. When the response signal is low, it is specified as a valid response bit (ACK), indicating that the receiver has successfully received this byte. When the response signal is high, it is specified as a non-response bit (NACK). Generally, it indicates that the receiver failed to receive this byte. The requirement for feedback of the effective response bit Ack is that the receiver lowers the SDA line during the low level before the 9th clock pulses, and ensure that the clock is stable during the high-level period. If the receiver is the master controller, after it receives the last byte, it sends an Nack signal to notify the controlled transmitter to end data transmission and release the SDA line, this allows the master receiver to send a stop signal p.

 

Insert wait time
　　If the controller needs to delay the time when the next Data byte starts to be transferred, the controller can wait by powering down and holding the clock line (SCL. Once the Controller releases the clock line, data transmission continues, giving the Controller enough time to transfer the received data bytes or prepare the data bytes to be sent. After the Controller with CPU responds to the received address byte, it takes some time to execute the interrupt service subroutine to analyze or compare the address code, in the meantime, we will place the SCL Wire Clamp on the low power level, and release the SCL line after proper processing, so that the main controller can continue to send data bytes later.

 

Bus blocking status
In special circumstances, blocking or disabling the bus is a feasible way to disable all communication activities on the I2C bus, as long as any device attached to the bus locks the clock-line SCL to the low-power flat.

 

Arbitration of bus Competition
There may be multiple devices attached to the bus. Sometimes two or more Main devices want to occupy the bus at the same time. This is called Bus competition. The I2C bus has the multi-control capability and can be used for arbitration of bus competition on the SDA line. The arbitration principle is as follows: when multiple master devices want to occupy the bus at the same time, if a primary device sends a high level, and another primary device sends a low level, the device whose sending level does not match the SDA bus level will automatically turn off its output level. The arbitration of bus competition is conducted at two levels.First, compare the addresses. If the master device is addressing the same slave device, it enters the data bit comparison to ensure the reliability of competition arbitration. Because the information on the I2C bus is used for arbitration, the information will not be lost.

Why is it identified that "0" will lose arbitration? Because the OD gate can only drive to the low level, the release bus can only be released through the non-driving bus, stop the driver to produce "1", but found that the bus is still "0 ", this indicates that the host is competing with itself for the right to use the bus. The host is driven to "1" and "0" is detected, which means that it has lost arbitration.

• The host can only start transfer when the bus is idle. Two or more hosts may have a starting condition in the minimum duration thd; Stas, and a specified starting condition is generated on the bus.
• When the SCL line is a high-power period, arbitration occurs on the SDA line. In this way, when other hosts send low-power periods, the host that sends a high-level Line Disconnects its data output level, because the bus level is different from its own level. Then, the judgment conditions are obtained:
• The arbitration can last for multiple places. First, compare the addresses. If each host tries to address the same device, the arbitration will continue to compare the data bit (assuming that the host is a sender) or compare the response bit (assuming that the host is a receiver ).
• The address and data information of the I2C bus are determined by the host that won the arbitration. No information will be lost during the arbitration process. A host that loses arbitration can generate a clock pulse until the end of the byte that loses arbitration.
• During serial transmission, the arbitration process is still in progress once repeated start or stop conditions are sent to the I2C bus. If this is possible, the host must send the duplicate start condition or stop condition at the same position in the frame format.
• In addition, if the host is combined with the slave feature and the arbitration is lost in the addressing phase, it is likely that the host won the arbitration in addressing devices. Then, the host that loses the arbitration must immediately switch to its slave mode.
• The control of I2C bus is only determined by the address, host code, and data sent from competing hosts. Without a central host, the bus does not have any customized priority.

It shows that the arbitration process of the two hosts may certainly include more content determined by the number of hosts connected to the bus. At this time, the internal data level of the host that generates data1 is different from the actual level of the SDA line. turning off data output means that the bus is connected to a high output level, which does not affect data transmission initiated by the host that won the arbitration.

Clock signal synchronization
The clock synchronization signal sent when information is transmitted on the I2C bus is completed by the logic "and" of all devices attached to the SCL line. The changes from high-level to low-level on the SCL line will affect these devices. Once the clock signal of a device switches down to a low-level, the SCL line will remain low, start the low-level period for all devices on the SCL line. At this time, the clock of a device with a short low-level cycle changes from low to high and does not affect the status of the SCL line. Therefore, these devices enter the status of a high-level wait. When the clock signals of all devices go up to high power, the low-level period ends, and the SCL line is released to return to the high level, that is, all devices start their high-level period at the same time. Then, the first device that ends the High-level period pulls the SCL line into a low-level device. In this way, a synchronization clock is generated on the SCL line.It can be seen that the clock low-level time is determined by the longest device in the clock low-level period, and the clock high-level time is determined by the device with the shortest time in the clock high-level period.