I2S and PCM

origin:http://blog.csdn.net/azloong/article/details/6536855

I2S Bus Specification

I2S (Inter-ic Sound) is a bus standard developed by Philips for audio data transmission between digital audio devices. In Philips's I2S standard, both the hardware interface specification and the format of digital audio data are stipulated. I2S has 3 main signals:

1, serial clock SCLK, also called bit clock bclk, that is, the corresponding digital audio every bit of data, SCLK has 1 pulses. SCLK frequency =2x Sampling frequency x sampling number of digits.

2, Frame clock Lrck, used to switch the left and right channel data. Lrck to "0" indicates that the left channel data is being transferred, and "1" indicates that the right channel data is being transferred. The frequency of the Lrck is equal to the sampling frequency.

3, serial data sdata, is the use of binary complement of the audio data representation.

Sometimes in order to better synchronize the system, you also need to transfer a signal MCLK, called the main clock, also known as the system clock (Sys Clock), is the sampling frequency of 256 times times or 384 times times.

No matter how many valid data are in the I2S format, the highest bit of data is always present at the 2nd SCLK Pulse after the Lrck change (i.e. the beginning of a frame), see the I2S format diagram below. This makes the receiver and the sender have a different number of significant digits. If the receiving end can handle less significant digits than the sender, you can discard the excess low data in the data frame, and if the receiving end can handle more significant digits than the sender, you can make up the remaining bits. This synchronization mechanism makes the interconnection of digital audio devices more convenient and does not cause data dislocation.

With the development of technology, there are many different data formats under the unified I2S interface. Depending on the position of the sdata data relative to the Lrck and SCLK, it is divided into left-aligned (less-used), I2S-format (i.e., Philips-defined format) and right-aligned (also known as Japanese format, normal format).

Non-I2S format as shown:

I2S format as shown:

For the I2S format, in order to ensure the correct transmission of digital audio signals, the sender and receiver should adopt the same data format and length. The data length can be different for the I2S format. and the frame clock Lrck high-low level corresponding to the meaning of the left and right channel is also different.

Note the difference between the I2S bus and the I2S format, the I2S Bus is a bus standard, and the I2S format is the data format developed by Philips. In the Unified I2S bus interface, there are non i2s formats such as left alignment and right alignment.

In our system Android, set the sample_rate=44.1khz,sample_length=16,channel=2; then BCLK should be 2x44.1khzx16=32xsample_rate, and actually mclk= 11.289MHZ,BCLK=MCLK/4,SAMPLE_RATE=LRCK=BLK/64=44.1KHZ,BCLK is inconsistent with the calculated value of the theory. Reference "If the receiving end can handle less significant digits than the sender, you can discard the excess low data in the data frame, and if the receiving end can handle more significant digits than the sender, you can make up the remaining bits", so this can be explained.

I2S/PCM Timing Comparison

Pcm

I2s

Dai Overview

Add AC97, I2S, PCM three interface descriptions, excerpted from kernel document DAI.txt:

asoc currently supports the three main digital audio interfaces  ( DAI)  found on   soc controllers and portable audio codecs  today, namely ac97, i2s and pcm.         ac97   = ===        ac97 is a five wire interface commonly  found on many PC sound cards. It is   now also  Popular in many portable devices. this dai has a reset line  and time   multiplexes its data on its sdata_out  (playback)  and SDATA_IN  (Capture)  lines.   the bit clock  (BCLK)  is  always driven by the CODEC  (Usually 12.288mhz)  and the    frame  (FRAME)   (usually 48khz)  is always driven by the controller. each  AC97   frame is 21us long and is divided into 13  time slots.      The ac97 specification can be found at  :-   http://www.intel.com/design/chipsets/audio/ac97_r23.pdf          i2s   ===       i2s is a common 4 wire dai  used in HiFi, STB and portable devices. The Tx and    Rx lines are used for audio transmission, whilst the bit  clock  (BCLK)  and   left/right clock  (LRC)  synchronise the  link. i2s is flexible in that either the   Controller or  codec can drive  (Master)  the bclk and lrc clock lines. bit clock    usually varies depending on the sample rate and the  master system clock   (SYSCLK).  lrclk is the same as the  sample rate. A few devices support separate   adc and  Dac lrclks, this allows for simultaneous capture and playback at    different sample rates.      i2s has several different  operating modes:-       o i2s - msb is transmitted  on the falling edge of the first BCLK after LRC            transition.       o left  justified - msb is transmitted on transition of lrc.        o right justified - msb is transmitted sample size bclks  before lrc                         transition.      pcm   ===       Pcm is another 4 wire interface, very similar to  I2S, which can support a more   flexible protocol. it  has bit clock  (BCLK)  and sync  (sync)  lines that are used    To synchronise the link whilst the tx and rx lines  are used to transmit and   Receive the audio data. bit  clock usually varies depending on sample rate   whilst sync runs at  the sample rate. pcm also supports time division   Multiplexing   (TDM)  in that several devices can use the bus  simultaneously  (this   is sometimes referred to as network mode).       common pcm operating modes:-       o mode  a - msb is transmitted on falling edge of first bclk  after FRAME/SYNC.       o Mode B - MSB is  transmitted on rising edge of frame/sync.