I2S Audio bus Learning (iii) I2S controller of S3C2440

I2S Audio bus Learning (iii) I2S controller of S3C2440 1. I2S controller structure diagram: Inter-IC Sound of s3c2440a (IIS) the bus interface is used as an encoding/decoding interface to connect external 8/16-bit stereo audio decoding IC for mini drive and portable applications. The IIS bus interface supports the IIS bus data format and MSB-justified data format. This interface replaces the interrupt with the DMA mode for FIFO access. It can receive and send data at the same time.

Figure 1 Structure Diagram

1. Bus Interface, register group and state machine (brfc): Bus interface logic and FIFO access are controlled by the state machine.
2. 5-bit double pre-timer (ipsr): one pre-timer is used as the main clock generator for the IIS bus interface, and the other is used as the external codec clock generator.
3. 64-bit FIFO (txfifo and rxfifo): when sending data, the data is written to txfifo; when receiving data transmission, the data is read from rxfifo.
4. Master iisclk generator (sclkg): In master device mode, the serial Bit Clock is generated from the master clock.
5. Channel generator and state machine (chnc): iisclk and iislrck are generated and controlled by the channel state machine.
6. 15-Position Displacement register (sftr): Transfers parallel data to serial data output in the sending mode and serial data input to parallel data in the receiving mode.

Ii. Sending and receiving mode 1. Normal Transmission

The IIS control register has a FIFO preparation flag for sending and receiving. When preparing to send data to the FIFO, if the FIFO is not empty, the FIFO preparation marks position 1. If the FIFO is empty, the position of the FIFO preparation flag is 0. When the receiving FIFO is not full, set the flag position to 1 for the receiving FIFO. It indicates that the FIFO is ready to receive data. If the received FIFO is full, set the FIFO preparation flag to 0. These flags are used to determine the CPU read/write FIFO time. This method can be used to send and receive serial data when the cup accesses and sends and receives FIFO data.

2. DMA Transmission

In this mode, the sending or receiving FIFO is accessible to the DMA controller. In the sending or receiving mode, the DMA service request is automatically executed by the FIFO preparation mark.

3. Sending and receiving modes

In this mode, the IIS bus interface can receive and send data at the same time.

Iii. Audio Serial Interface Format 1.iis bus format

The IIS Bus consists of four lines, including serial data input (iisdi), serial data output (iisdo), left and right channels (iislrck), and serial Bit Clock (iisclk ). The devices that generate iislrck and iisclk are the primary devices. Serial data is sent with a 2's complement code, and MSB (most significant bit highest bit) is first sent. Because the transmitter and receiver may have different word lengths, MSB (highest bit) is first sent. The transmitter does not have to know how many BITs can be processed by the receiver or how many bits will be received by the receiver. When the system font length is greater than the generator font length, the word is truncated for data transmission (the limit is set to 0 ). If the receiver receives a bit larger than its font length, the bit after the LSB is ignored. In addition, if the number of digits received by the receiver is smaller than the font length, the missing bit is set to 0. Therefore, MSB
There is a fixed position, and the position of LSB depends on the word length. As long as the iislrck sends a change, the sender sends the MSB of the next word within a clock cycle. The serial data sent by the sender can be synchronized with the falling edge and rising edge of the clock signal. However, serial data must be locked in the rising edge of the serial clock signal to the receiver. Therefore, when the data on the rising edge of synchronization is sent, there are some restrictions. The left-side channel selection line specifies the channel being sent. Iislrck can be changed in the descent or rising edge of the serial clock, but it does not need to be symmetric at that time. In the slave device, the signal is locked in the descent or rising edge of the serial clock. When MSB is sent, the iislrck line changes the clock cycle. This allows the sender to export the serial data synchronization sequence used to establish the transmission. In addition, it enables receiving of the previous word and clearing the input for receiving the next word.

2. MSB justified format

MSB justified bus format is structured and IIS bus format. The difference between the unique and IIS Bus formats is that the MSB justified format enables the sender to always send the MSB of the next word as long as the iislrck changes.

Figure 2 IIS format and MSB justified data format 4. IIS collection frequency and master device clock

The clock frequency of the I2S main device can be selected through the sampling frequency, because the clock frequency of the I2S main device is generated by the I2S divider (the clock frequency of the main device = pclk/pre-divider value ), therefore, you must select the appropriate pre-division value and codeclk sampling frequency type (256fs or 384fs) to obtain the appropriate i2slrck frequency (i2slrck frequency = clock frequency of the master device/codeclk ).
The serial bit uses the frequency type (16/32/48fs) you can configure the serial number of digits and codeclk sampling frequency type of the channel (Serial bit clock frequency type = codeclk adopt type/serial number of digits ).

V. Special Registers for IIS bus interfaces

I2S-related registers include I2S control register i2scon, I2S mode register i2smod, I2S Frequency Register i2spsr, i2sfcon register, and FIFO register.

1) i2scon control register

The physical address of the i2scon control register is 0x55000000, which can be read/written. The Value After resetting is 0x100. The meaning of each bit in the register is as follows:

[8] Left and Right channels, 0 = left channels, 1 = right channels;
[7] sending the FIFO readiness mark. If 0 is used, it indicates that it is not ready. If 1 is used, it indicates that the FIFO is ready;
[6] receives the FIFO readiness mark. If 0 is used, it indicates that it is not ready. If 1 is used, it indicates that the FIFO is ready;
[5] Send DMA request enabling. If the value is 0, the request is forbidden. If the value is 1, the request is enabled;
[4] receives DMA request enabling. If the value is 0, the request is forbidden. If the value is 1, the request is enabled;
[3] sending channel idle command. When idle (paused), i2slrck is not activated, 0 indicates i2slrck is generated, and 1 indicates no;
[2] receive channel idle command. When idle (pause transmission), i2slrck is not activated, 0 indicates i2slrck is generated, and 1 indicates no;
[1] Enable I2S pre-divider. If the value is 0, the pre-divider is disabled. If the value is 1, the pre-divider is enabled;
[0] I2S interface enabling. If the value is 0, I2S is disabled. If the value is 1, I2S is enabled.

2) i2smod mode register

The physical address of the i2smod mode register is 0x55000004, which can be read/written. The Value After resetting is 0x000. The meaning of each bit in the register is as follows:

[8] Master/Slave Mode selection. The master mode is set to 0, and the slave mode is set to 1;
[] Select sending/receiving mode, 00 = none, 01 = receiving mode, 10 = Sending mode, 11 = Sending/receiving mode;
[5] the priority of the left and right channels. If the value is 0, the right channel height is low. If the value is 1, the right channel is low and the left channel height is high;
[4] Serial Interface format. The I2S compatible format is set to 0, and the MSB adjustable format is set to 1;
[3] serial data bits per channel. Values: 0, 8, and 1, 16;
[2] select the master clock frequency. When the value is 0, the master clock is 256fs (sampling frequency), and the value is 384fs when the value is 1;
[1:0] serial bit clock frequency selection, 00 = Bit Clock is 16fs, 01 = Bit Clock is 32fs, 10 = Bit Clock is 48fs, 11 = undefined.

3) I2S frequency division register i2spsr

The physical address of the I2S sub-register is 0x55000008, which can be read/written. The Value After resetting is 0x000. The meaning of each bit in the register is as follows:

[] A pre-division value, division factor of A, I2S Bus Interface main clock = mclk/a pre-division factor;
[4: 0] B Pre-division value, division factor of pre-Division B, external codec clock = mckl/B Pre-division factor.

4) i2sfcon register

The physical address of the i2sfcon register is 0x5500000c, which can be read/written. The reset value is 0x000. The meaning of each bit in the register is as follows:

[15] select the sending FIFO access mode. If the value is 0, the operation is in normal mode, and if the value is 1, the operation is in DMA mode;
[14] select the receiving FIFO access mode. If the value is 0, the operation is in normal mode, and if the value is 1, the operation is in DMA mode;
[13] control the sending FIFO enable. If the value is set to 1, it is disabled when the value is set to 0;
[12] control the receiving FIFO enable. If this parameter is set to 1, it is disabled when it is set to 0;
[11: 6] sending-side FIFO data count, with a Count value of 0 ~ 32;
[] The number of FIFO data records on the receiving end is 0 ~ 32.

5) FIFO register i2sfif

The physical address of the FIFO register is 0x55000010, which can be read/written. The reset value is 0x000. The meaning of each bit in the register is as follows: the I2S bus interface has two 64-byte FIFO in the sending/receiving mode, each of which consists of a table with a width of 16 and a depth of 32, in addition, each FIFO unit can operate on high or low bytes respectively. Access the sending and receiving FIFO through the FIFO entry. The entry address is 0x55000010.