IBM DB2 Enterprise 9 performance with power5+ and AIX 5L multi-page support

Learn how ibm®db2®9 for linux®, unix®, and windows® (DB2) Take advantage of multiple page sizes (multiple page size). With the introduction of the Power5+™ processor architecture, the IBM AIX 5l™ operating system has added support for the new KB page, which is similar to the current default 4 KB page. In addition, the AIX 5L Version 5.3 TL04 has introduced a new GB Mega page feature for this hardware architecture. DB2 9 automatically leverages the KB page to provide high performance for database applications on the platform. In addition, DB2 also supports the use of GB mega pages.

Brief introduction

For a variety of reasons, most modern operating systems run programs in the virtual address space. Virtual addresses have many advantages, including flexibility, independence, portability, and more addressing space than physical memory, and to some extent allow for the independence of the underlying hardware configuration.

However, running a program in a virtual address space can also have a corresponding cost. The memory address referenced by the program (including DB2) is a virtual address. Each time a program instruction or data processing memory location is required, the virtual address is converted to a physical (or actual) memory address. This conversion is maintained by a page table, which increases the execution time of the program. The size of the page table is inversely proportional to the size of the page, which means that the smaller the page size, the larger the page table and the greater the overhead.

For years, 4 KB has been a standard page size for most operating systems, including the AIX 5L operating environment. Recently, the 4 KB page size has become somewhat inefficient as data volumes and processor addressable memory have increased. To improve the performance of applications that handle large amounts of data, multiple page size support is introduced for systems that are based on IBM power5+ processors and running AIX 5L V5.3 TL04 (or later). Starting with the Aix 5L V5.1, the power™ processor and the AIX 5L operating system support two page sizes (4 KB and MB). In addition to these two page sizes, the most recently available page sizes are in kilobytes and GB. Pages in kilobytes are the same behavior as 4 KB. (That is, these page memory is not fixed and can be paginated.) ）

To take advantage of the latest available page sizes, DB2 9 automatically detects the available page sizes in the system. If the 64KB page size is available, then DB2 sets the default size of some processes and all shared memory areas to kilobytes. Starting with the IBM DB2 Universal database™ (UDB) V8.2.5, DB2 also adds support for the GB page.

Background knowledge

Let's look at the process runtime environment to see why large pages are so valuable to enterprise applications such as DB2.

Process run time environment

Before running any program, the operating system loader must load it into the actual memory. In the AIX 5L environment, the memory used to run the process is divided into various memory regions. Private areas for processes are: text, stack, and Data/heap, each region dedicated to a particular purpose:

Text area stores the instructions for the process.

The Data/heap zone contains dynamically allocated memory and globally accessible program data (such as DB2 proxy private memory).

The stack area is used for subroutine return addresses and for storing automatic data.

There is also a private area called shared memory, which is a widely used interprocess communication mechanism in DB2 and other multi-process applications. DB2 uses shared memory areas to efficiently process and share data between collaborative DB2 processes, such as DB2 proxies, primarily for buffer pools. DB2 also uses shared memory for a variety of other heaps.

As mentioned earlier, the memory address referenced by the process is a virtual address and needs to be converted to a physical address. For each running process, the mapping between the virtual address and the physical address is maintained in a data structure called a page table. The number of page tables is proportional to the size of the virtual address space. As a result, the size of the page table is important. To expedite address translation, there is a processor-on-a-chip (PoC) cache and associated transformation fallback buffer (TLB) logic in the schema. A TLB is a small cache area that stores the most recent address translation for reuse.

Advantages of large pages

In addition to the processor clock speed, another important processor performance metric is the clock cycle (CPI) for each instruction. In fact, CPI is a measure of how long it takes to run an instruction. The usual CPI refers to the average or normalized CPI. The lower the CPI, the faster the execution, the better the performance.

TLB Cache entry Reuse (cache hit) means faster address translation, and also means faster access to physical memory. If the TLB does not hit, then the page table stored in main memory needs to be accessed, which consumes a considerable amount of processor cycles. Increasing the address space of the process (that is, increasing from 32-bit address space to 64-bit address space) has become more common, but it will increase the size of the page table and thus reduce the speed of address translation.

To solve this problem, there are two options. One option is to increase the TLB size. However, due to the limitations of the chip space, the TLB size cannot be increased proportionally. Another option is to reduce the size of the page table by reducing entries in the page table. As noted earlier, the page table size is inversely proportional to the page size, which means that increasing the page size can make the page table smaller, and that each TLB entry can accommodate more address conversions. (that is, the wider the page, the more information each page stores.) ）

The power5+ processor architecture (running the AIX 5L operating system) solves page table problems by introducing multiple page sizes. An application can choose a page size that matches the size and attributes of its workload. As you'll see later in this article, this idea can produce considerable performance benefits.

AIX 5L Multi-page size support

This section provides a brief overview of the multiple page size support for AIX 5L. As mentioned in the Introduction section, the power5+ processor and the AIX 5L V5.3 (with 5300-04 recommended technical levels) have introduced support for two new virtual memory page sizes: MB and GB. GB pages are used only for very high performance environments, while the pages in kilobytes are designed for general purposes. In fact, for most workloads, a page with a KB is better than a 4 KB page. We'll discuss later in this article the performance benefits of using a page with DB2. The allocation of GB pages requires the IBM hardware Management Console (HMC) Version 5 Release 2 machine code.

When you run the 5300-04 technical-level 64-bit AIX 5L kernel on a power5+ processor-based system, support for the KB page size is automatically enabled and does not require system configuration or tuning.

Note that the full KB page can be paginated, and the pool size of the KB page frames is dynamic. The AIX 5L operating system manages the size of the pool and changes the number of 4 KB and KB page frames according to the needs of the different page sizes. However, the MB page size requires the use of the VMO command to configure the AIX 5L.

You can use the AIX 5L Svmon and Vmstat commands to monitor the number of 4 KB and KB page frames on your system. For example, to display DB2 process statistics about each page size, you can use the-P flag, the DB2 process ID (PID), and the Svmon command:

# svmon –P 852128
-------------------------------------------------------------------------------
　　 Pid Command　　　　　Inuse　　　Pin　　 Pgsp　Virtual 64-bit Mthrd　16MB
　852128 db2sysc　　　　 372534　　65669　　　　0　 371671　　　Y　　 N　　 N
　　PageSize　　　Inuse　　　　Pin　　　 Pgsp　　Virtual
　　 s　 4 KB　　　 4521　　　　　0　　　　　0　　　 3657
　　 m　64 KB　　 302477　　　　133　　　　　0　　 302478
　 Vsid　　　Esid Type Description　　　　　　　PSize　Inuse　 Pin Pgsp　Virtual
　　　 0　　　　 0 work kernel (lgpg_vsid=0)　　　　 L　65536 65536　　0 65536
　　　　　　　　　 Addr Range: 0..65535
　2e845f　78000048 work default shmat/mmap　　　　　 m　 4096　　 0　　0　4096
　　　　　　　　　 Addr Range: 0..4095
　1987b1　78000021 work default shmat/mmap　　　　　 m　 4096　　 0　　0　4096
... output snipped ...