IC Power Management Unit

The main functions of power management power supply inside the chip are described as follows:

* Reset

* Phase-locked loop and divider

* HWCFG[2:0] PIN signal recognition and decoding

* Sleep mode

* Module Power Management

* Top Level control register

First, reset

The reset signal source has the following types:

1, Pin_resetn(Low Effective): PIN_RESETN will return the entire chip to the default state

2, Pin_a11strst(Low Effective): Pin_a11strst is usually connected to ARM debugging tool, it can recover most of the chip module (except the following modules):

A, ARM coprocessor CP14 debug Logic

B, Phase-locked loop

3, watchdog Reset: In addition to the software configuration register SWRSTR other will be reset

4, SWRSTR Register Reset: In addition to itself is not reset, the other will be reset

second, phase-locked loop

There are 5 phase-locked loops in the chip:PLL1, PLL2, PLL3, Pllm and PLLA

* PLL1 and PLL2 are universal phase-locked loops

* PLL3 is a special high-speed phase-locked loop

* PLLM is a universal phase-locked loop dedicated to Mddr

* PLLA is a high-speed phase-locked loop dedicated to ARM CPUs

1. Universal phase-locked loop

The following is a general-purpose phase-locked loop (PLL1, PLL2, pllm) structure diagram

The Clkin is the input clock (usually 26M). The Clkin provides a 13M reference clock to the phase-locked loop via the input divider, and if the input clock is 13M, a sel_13m 1 is required to bypass the input divider. The feedback divider of the PLL is controlled by the FDIV, and the output divider will be divided into 1, 2, 4, 8, Fvco by odiv[1:0]. When sel_13m = 0 o'clock, the output clock frequency is calculated as follows:

When BYPASS = 1, the output clock equals the input clock. When pwrdn = = 1, the phase-locked loop is closed. The Fvco frequency range for PLL1, PLL2, and Pllm is [650m,1300m], which is the range of FDIV (50,100]. The QP, VCO, and D2C control the current inside the phase-locked loop.

2, high-speed phase-locked loop

The following is the structure of the high-speed phase-locked loop (PLL3, PLLA)

The control signal of the high-speed phase-locked loop is basically consistent with the universal phase-locked loop, and the output clock frequency is as follows:

3. Crossover Device

The array circuit has a 40-component frequency (D0-D39), and the analog circuit has a 8-component frequency device (A0-A7). Each divider can be programmed to set the input clock (PLL1, PLL2, PLL3, crystal, external clock ), and the output clock divides the input clock by n,n to the register value [1, 32]. The default state of the chip will open all dividers, and the software must turn off unnecessary dividers to reduce power dissipation when appropriate, and some dividers provide a lower output frequency through cascading methods. The divider is set by the corresponding register, and the hardware circuit automatically ensures that the instantaneous clock changes when the clock is changed by a state machine without affecting the downstream logic. No other registers on the AHB bus can be accessed until the hardware state machine is complete, which is approximately 160 crystal clock cycles. The following are the default settings for each clock in 000-011 four startup modes:

The src_sel:0 is a crystal clock, 1 is PLL1, and 2 is pll2,3 for PLL3. In addition, the clock source of the peripheral is provided by D17 control, or Clk_app .

Three, HWCFG mode selection

The operation mode of the chip is selected by pin_nddat[2:0] , which can be controlled by pulling up and down, and the list of all modes is as follows:

Boot from NAND

001 UART Download

010 Boot from SD

011 Boot from MSD

Reserved

101 PLL Bypass (boot from NAND)

External Boot

111 External boot (debug bus enabled)

Four, sleep mode

The processor goes into sleep mode to reduce power consumption, and in sleep mode, the core clock of ARM and the AXI bus will be shut down until the interrupt wakes the processor. When the processor sleeps, you can set the app bus to shut down via the register. The same L2 cache will be closed when the processor sleeps, so the software needs to synchronize the L2 cache before sleep. Here is the sequence of operations in which the processor enters and exits sleep:

A. Set interrupt events to wake the processor (usually a timer or GPIO)

b, set ARM configuration register armcfgr bit0 for 1 to start the sleep process

C, execute the WFI instruction , this instruction will let arm perform the necessary operation to enter the standby mode safely, once arm enters standby mode, the STANDBYWFI mark will be placed Armcfgr bit1

D, close ARM clock, hardware tag arm_sleep will be set ARMCFGR bit2

E, when the wake-up interrupt arrives, the arm_sleep tag will be cleared, the arm clock will open, and then arm exits standby mode into run mode

Baseband Sleep , the Stach processor and PHY processor will go to sleep independently, and the corresponding status token can be obtained from the PMSTATR register. To maximize power savings, the chip can enter deep sleep mode, and all PLL circuits and clocks in deep sleep mode will be turned off, with only 32.768 KHz clocks present. During deep sleep, the processor can control the external PMU through a GPIO to enter a low-power mode.

In deep sleep mode, the DDR Self-refreshcan be controlled by programming the DDR controller to enter the automatic low-power mode, in which the DDR controller will turn on the DDR if it does not receive active operation within the specified clock cycle. Self-fresh and set the Cke_status tag, the processor will wait until deep sleep until the mark is placed, when exiting deep sleep, the first time to open the DDR clock and wait until the DLL stable, and then open the clock of the other modules, DDR control will be in the first access to the DDR Data, Exit Self-fresh. In deep sleep mode, you can still specify some clocks to remain open, such as USB. Here is the state machine for deep sleep:

v. Module Power Management

Some function modules inside the chip have built-in power switch, can be opened or closed independently, these modules include:arm_cpu, DSP, Mm_ge, they can be controlled by register ARMPWDR, DSPPWDR, MMGEPWDR.

The closing process for ARM is as follows: first set ARMPWDR. SLEEP_PWD is 1 and then starts the normal sleep flow of arm, when Arm_sleep is set, the Power management unit will automatically close arm until the wake-up interrupt arrives. When ARM is power up again, ARM will be reset and executed from the address 0x0 .

six, top-level control register

* Clock Control Register

* USB PHY Controller

* Baseband top-level control register

* Analog front-end top-level control register