IIC Protocol Interpretation

IIC Protocol Interpretation

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(1) Overview

I²c (inter-integrated Circuit bus) integrated circuit bus, which is designed by NXP (formerly Philips), is used for master controller and slave-to-device communication, in small data volume occasions, transmission distance is short, at any time can only have one host and other features.

Often IIC and SPI interfaces are considered to be designated as a hardware device, but in fact such a statement is not accurate, strictly speaking, they are defined as a soft and hard combination, divided into physical layer (four-wire structure) and protocol layer (host, slave, clock polarity, clock phase).

The difference between IIC,SPI and the physical layer, IIC has a more complex set of protocol layer definitions than the SPI. The physical layer and protocol layer of IIC are explained below separately.

(2) The physical layer of IIC

A Only two bus lines are required, one is the serial data line SDA, and one is the serial clock line SCL. (IIC is half-duplex, not full-duplex).

B. Each device connected to the bus can communicate through a unique address and other devices, the host/slave role and address can be configured, the host can act as the host transmitter and host receiver.

C.IIC is a true multi-host bus, (and this SPI in each communication before the host must be dead, and IIC can in the communication process, change the host), if two or more hosts simultaneously request the bus, can be through conflict detection and arbitration to prevent the bus data is destroyed.

D. The transmission rate can reach 100kb/s in standard mode, and 400kb/s can be reached in fast mode.

E. The number of ICS connected to the bus is limited only by the maximum load capacitance of the bus 400pf.

A typical IIC interface as shown in (1)

Figure (1)

(3) The protocol layer of IIC

IIC protocol layer is the key to Master IIC. Now briefly summarize as follows:

A. Validity of data

In the high cycle of the clock, the data on the SDA line must remain stable, and the data line can only be changed at a low clock SCL. Except as a start/end condition.

(2) Shown:

Figure (2)

B. Start and end conditions

starting condition : When the SCL is high, the high-to-low jump on the SDA line is defined as the starting condition, the end condition : When the SCL is high, the low to high jumps on the SDA line are defined as the stop condition, note Start and stop signals are sent by the host, connected to the I2c bus device, if i2C the hardware interface of the bus, it is easy to detect the start and stop signals. the bus is considered busy after the starting condition, is considered idle after the stop condition, and the description of the starting and ending conditions is shown in (3).

Figure (3)

C. Response

Whenever the host sends a byte of data to the slave, the host always waits for the slave to give a response signal to confirm that the slave has successfully received the data, and the clock required by the slave answering host is still provided by the host, and the response appears at the clock cycle that follows each time the host completes 8 data bits transmission. , a low level of 0 means answer, 1 is non-answer, and (4) is shown.

figure (4)

D. Data frame format

The data signals transmitted on the I²C bus are generalized, including both the address signal and the real data signal. after the starting signal must be transmitted a slave address (7 bits), the 8th bit is the data transfer direction bit (r/t), with "0" for the host to send data (T), "1" indicates that the host receives data (R)。 {This small part in the drive MPU6050 module, it made such a mistake, it writes the MPU6050 from the machine address is 0x68, because when sending the slave address, to add a read and write direction bit, because the beginning should be to this MPU6050 to write a register from the machine address, So it should be 7-bit address 0x68 (1101000) + bits 0=11010000) that is 0xd0, means to write to the IIC device, and then then write to the IIC device register address, and I directly write to 0x68, resulting in an error}, Each data transfer is always ended by a terminating signal generated by the host. However, if the host wants to continue to occupy the bus for new data transfer, it can not produce a stop signal, immediately again send the start signal to another slave to address. In the process of one-time data transmission of the bus, there are several combinations of the following methods: [1]The host sends data to the slave, and the data is transferred in the same direction throughout the transfer process: (write mode) Note: A shaded section indicates that the data is transmitted from the host to the slave, and no shaded parts indicate The data is transmitted from the slave to the host . A indicates an answer (low level), A non-indication non-response (high level). S indicates the starting signal, P represents a stop signal. [2] The host reads the data from the slave machine immediately after the first byte: (read mode)
[3] in the transmission process, when the transmission direction needs to be changed, the start signal and the slave address are repeated once, but two read/write direction bit exactly reversed: (Read and write switching mode)
Note: No incoming reply is required at the end of the read mode. In general, [3] is more common, such as the MPU6050 module: sends the start signal to wait for the slave to answer(? Need to see the next MPU6050 manual)Write a Slave address +0 (write), wait for a slave answer to send a byte of the MPU6050 Acceleration Storage register address, wait for the slave to answer and then send a start signal to wait for the slave answer to write a slave address +1 (Express read) waiting for slave to read the MPU6050 sensor data host non-answer simulation of E.IIC signalThe host can adopt the single-chip microcomputer without the I²C bus interface, such as 80C51, at89c2051 and other SCM, using the software to realize the data transmission of the I²C bus, that is, the combination of software and hardware signal simulation. Even the single-chip microcomputer with IIC hardware (such as the Stm32 103 series) has some drawbacks, sothe timing of the IIC is also generally simulated。 The specific time is as follows:

IIC Clock frequency: no higher than 400K

Answer: When the IIC host (not necessarily the sender or the receiver) sends out the 8-bit data or command, the SDA signal is set as input, waiting for the Slave to answer (wait for SDA to pull low from high level)

If the slave is correctly answered, indicating that the data or command transmission is successful, otherwise the transmission fails, note that the response signal is the data received imagining sent to the sender.

IIC Device Address: Each IIC device has a device address, and some device address at the factory address is set, the user can not change, such as OV7670

The address is 0x42. Some devices such as EEPROM, the first four addresses have been identified as 1010, the last three addresses are determined by the hardware link, so a

An IIC bus can connect up to 8 EEPROM chips.

After the signal is started on the figure, the seven-bit address represents the device address, the eighth digit reads or writes (0 is write, 1 is read), and then the response bit.

IIC device Single-byte write timing:

IIC Device multibyte address write sequence : Multibyte address is more than a single-byte address in the timing of a write address

single-byte device read timing : Note that the final generation of no response signal, the other multi-byte address read sequence is similar to a single byte, just a few more address bytes.

Three major serial buses: UART, SPI, IIC

Sync: SPI Async: Iic,uart

Synchronous and asynchronous differences: whether the acquisition of data is using the clock along, if it is the clock along the mining data, synchronous transmission, if the level of data acquisition is asynchronous

The serial port accepts the data is actually a serial turn and the process

The specific program code is as follows:

//generate a start signalvoidI2c_start (void) {i2c_sda_out ();//Configure PIN, PIN set to outputi2c_sda_h;//pull up the data lineI2c_scl_h;//pull the clock line highDelay_us (5);//5 μs delay, more than 4.7 microseconds requiredi2c_sda_l;//pull down, produce falling edgeDelay_us (6);//This process is greater than 4 microsecondsi2c_scl_l;//Finally, be sure to pull down this clock line because only the clock line is pulled down to allow data changes. }//Generate stop SignalvoidI2c_stop (void) {i2c_sda_out ();   i2c_scl_l;   i2c_sda_l;   I2c_scl_h; Delay_us (6);   I2c_sda_h; Delay_us (6);}//The host generates an ACK for the response signalvoidI2c_ack (void) {i2c_scl_l;   I2c_sda_out ();   i2c_sda_l; Delay_us (2);   I2c_scl_h; Delay_us (5);  i2c_scl_l;} //The host does not generate a response signal nackvoidI2c_nack (void) {i2c_scl_l;   I2c_sda_out ();   I2c_sda_h; Delay_us (2);   I2c_scl_h; Delay_us (5); i2c_scl_l;}//waiting for the slave to answer the signal, we only responsible for the host response signal generation, from the machine to answer the signal//we don't control it. //return Value: 1 receive reply failed//0 Receive answer succeededU8 I2c_wait_ack (void) {U8 Temptime=0; I2c_sda_in (); //configured as a pull-up input. I2c_sda_h;//the host releases the data bus and waits for the slave to generate a response signalDelay_us (1);    I2c_scl_h; Delay_us (1); //waits for the slave to operate the data bus. Low-level rep answer     while(Gpio_readinputdatabit (GPIO_I2C,I2C_SDA)) {Temptime++; //This belongs to software delay, not necessarily accurate.         if(temptime> -)//if time times out, stop without answering. {i2c_stop (); return 1;//returns 1 if there is no response.}} i2c_scl_l; return 0;//If there is a response, return 0.}    

For different IIC equipment, IIC protocol may have a certain difference, and some address need to move left one, the lowest bit free to do read and write bits. Reference: https://www.cnblogs.com/zhangjiansheng/p/7738390.htmlhttps://www.cnblogs.com/bixiaopengblog/p/7469536.html

IIC protocol Interpretation (RPM)